Phase delay at 2Msps between ADC channels on Tm4c129x

Hello PAk,

Some data/info needed here

1. What is the high speed frequency you are measuring here? It must not exceed Nyquist theorem,

2. What is the source resistance as seen by the ADC on the two channels? If it is more than the what is spec-ed in the electrical section of ADC for Rs, then you may want to use the Sample Hold Register to increase the sampling time. It will reduce the sampling rate though.

Regards

Amit

PAk said:

However, at high input frequencies we are watching some delay between them (not appreciable at lower freq).

 Hi PAk, maybe AMIT don't catch from your writing you are using just one ADC, is this correct?

 If so then the delay are you experiencing is due to time of conversion sequence first/second channel.

 If you are firing both ADC then please specify better.

I agree w/Roberto regarding the "natural" delay - between the measurement of any 2 input signals - w/in the same ADC sequence.

That said - I can't agree that Amit "missed" anything - his response seems fine.

To exploit the phase capability of past LX4F and "plain vanilla" 4C123 - were not 2 ADC modules required to be, "enabled and placed in play?"   Your code does not reveal such - in fact your verbage indicates just a single ADC module.  (ADC0)

We've long found that such "serious testing" of ADCs (be they MCU constrained or "real" external ones) benefits immensely from driving the ADC inputs with a properly spec'ed, linear voltage ramp.  (with both frequency and ramp shape under quick/eased/precise control.)   Your test may too often be "contaminated" by your source proving "out of spec to the ADC" - or not behaving in the manner which best reveals ADC hiccups or weakness.

I vote - once more - for a properly designed/spec'ed linear ramp as "best for this ADC analysis!"  The linear ramp enables your easy prediction of exactly what measure the ADC should capture - at very predictable (i.e. "linear" points in time!)   All other methods - in our investigations - fall short...

One more point - suspect of value to those landing here - interested in "serious" ADC design/development.  Mixed signal devices - such as MCUs here/elsewhere - often are unable to match the speed, accuracy and robustness of, independent, "dedicated ADCs."  And that's to be expected - is it not?

So - would your test not improve/be speeded by your acquisition of a serious, external ADC?  Running your stimulus and/or test signals first into that "pro" ADC may better insure that those stimulus/test signals are indeed, "A-Ok."  Present method - "assume/pray" that they're proper - harks back to the dayze of "one-way" RS232 - otherwise known as, "Send & Pray!"  Your present method employs your MCU's ADC as both, "judge & jury."  My sense - you've too many "variables in play" better to limit, systematically reduce that number - proceed by refinement... (always)

Roberto Romano said:

 Hi PAk, maybe AMIT don't catch from your writing you are using just one ADC, is this correct?

 If so then the delay are you experiencing is due to time of conversion sequence first/second channel.

 If you are firing both ADC then please specify better.

You are right, I am using one ADC, only on ADC0. 2 channles at 800kHz each.

Amit Ashara said:

Some data/info needed here

1. What is the high speed frequency you are measuring here? It must not exceed Nyquist theorem,

2. What is the source resistance as seen by the ADC on the two channels? If it is more than the what is spec-ed in the electrical section of ADC for Rs, then you may want to use the Sample Hold Register to increase the sampling time. It will reduce the sampling rate though.

1. We are not exceeding Nyquist (we are sampling until 300kHz with a 800kHz sampling freq on 2 channels)

2. Our equivalent Rs on the ADCs is around 110 ohm. 

Hello PAk,

Roberto is right. The Phase Shift sampling is only applicable when the two ADC's are used together to sample the same channel.

Also the Rs per channel is also fine as it below the 500 ohms requirement. What would be useful is a plot of the signal and the sampled data, to see visually what is being sampled (if the signal is periodic).

Do note that the ADC would be making ~3 measurements for the signal.

Regards

Amit

Amit Ashara said:

Do note that the ADC would be making ~3 measurements for the signal.

Which 3 measurements?

Amit Ashara said:

What would be useful is a plot of the signal and the sampled data, to see visually what is being sampled (if the signal is periodic).

This is a 40kHz sin wave (from a dirty generator) sampled signal.

Here you can see the phase difference, which happens to be "0.25-sample" delay.

You can spot a difference of 3 dB of image carrier)

Let's see

2Msps conversion rate

• 800ksps sampling rate per channel
• 2 channels on same converter
• resulting in an effective 1.6Msps rate

Does that correctly summarize what you are doing?

At 2Msps conversion rate you would expect a value every 0.5 uS.  The sampling interval at 800ksps is 1.25us so you would expect a sampling offset of 0.5/1.25 = 0.4 of a step.  You are correct, a phase delay of 0.25 of a sample period appears low but is your test accurate enough to capture that difference?  It's not clear to me how you are determining that phase difference.

Robert

Hello PAk,

If the phase difference is the issue then I would support Zhang's statement on using both the ADC's with the common trigger.

If the real issue is why there is a phase difference, then perhaps a code post would be useful for us to re-create the same and then check w.r.t the code execution of the computations.

Regards

Amit

Robert Adsett said:

  The sampling interval at 800ksps is 1.25us so you would expect a sampling offset of 0.5/1.25 = 0.4 of a step.  You are correct, a phase delay of 0.25 of a sample period appears low but is your test accurate enough to capture that diffe

Actually I was thinking 1.25 - (2 samples*500ns) = 0.25 step. Maybe it is better explained your way.

Amit Ashara said:

Hello PAk,

If the phase difference is the issue then I would support Zhang's statement on using both the ADC's with the common trigger.

If the real issue is why there is a phase difference, then perhaps a code post would be useful for us to re-create the same and then check w.r.t the code execution of the computations.

It is simpler than that Amit....the question is:

Is it possible to synchronize 2 channels triggered by a timer on one ADC?

The way Zhang has said it is one way to solve this issue, but we wouldn't like to use the second ADC for this.

Regards.

cb1- said:

Is it possible to synchronize 2 channels triggered by a timer on one ADC?

Glance at the ADC block diagram - w/in MCU manual - reveals critical, single cap which must be - sequentially - charged then discharged.  That should quickly reveal - and thus is the real answer - to your goal of, "multi-channel, sync'ed acquisition" via a single ADC.

Second ADC module contains 2nd cap - thus enables two channels to be (near) simultaneously acquired.

The ADC chapter w/in this maker's MCUs is reasonably well detailed - too much time @ the IDE - not enough RTFM - leads to such issues...

Unrevealed is "why" you need to hold the 2nd ADC away from this usage.  Might it be possible to "steal" that 2nd ADC module - for just those times when you need to harvest, "2 channel, sync'ed analog data?"  After that acq - you can divert module 2 to normal usage."

[/quote]

Actually I read it, but it was not stated as clear as I supposed...that is the aim of asking ;)

cb1- said:

Unrevealed is "why" you need to hold the 2nd ADC away from this usage.  Might it be possible to "steal" that 2nd ADC module - for just those times when you need to harvest, "2 channel, sync'ed analog data?"  After that acq - you can divert module 2 to normal usage."

I am sampling all the time, and need to sample other data from other sensors. Maybe I could live with this issue on the spectrum dimension.... but that is a good one.

Clear to me is now, why other ARM MCU implement 3 ADC modules (an odd number)

cb1- said:

Note that vendor here "illustrates" their ADC performance via, "admittedly noisy" signal.  Linear ramp - as past suggested - enables, "predictable - real and clean" signal captures - does not "camouflage" potential (or likely) ADC errors...

Didn't get this one.

PAk said:

why other ARM MCU implement 3 ADC modules (an odd number)

We've had 2 sales-folk (different vendors) speak of "4" ADC Modules!   Progress, progress...

You see now why our group uses ARM from multiple vendors (some here).  The new Cortex M0 is available in very small, extremely low cost versions - that may best enable your requirement for more massive - ADC harvest!

Thank you for the neat Verify Award...  (and beware "proof" - garnered via less than sterling signal sources...)

cb1- said:

why other ARM MCU implement 3 ADC modules (an odd number)

We've had 2 sales-folk (different vendors) speak of "4" ADC Modules!   Progress, progress...

You see now why our group uses ARM from multiple vendors (some here).  The new Cortex M0 is available in very small, extremely low cost versions - that may best enable your requirement for more massive - ADC harvest!

Thank you for the neat Verify Award...  (and beware "proof" - garnered via less than sterling signal sources...)

[/quote]

I need more power than M0 (of course a multiprocessor would do it)

This is when I think out loud, which is the roadmap of TI for Tiva.....and probably silence will be the answer

PAk said:

Didn't get this one.

You're surely smart/experienced enough to get it!

Linear ramp - triggered to rise from 0V0 - at exactly the time you seek - progresses uniformly/predictably.  By logging the ADC's harvest (say 8 sequence capture) it is quite simple to determine the ADC's "Acquisition Time Sequence" and the ADC's accuracy.   Much is revealed via such disciplined test.

Using a "dirty generator" - on the other hand - proves what?  (some - not moi - may suggest this camouflages errors.  Recall I'm simple reporter - conclusion left for others)

cb1- said:

Didn't get this one.

You're surely smart/experienced enough to get it!

Linear ramp - triggered to rise from 0V0 - at exactly the time you seek - progresses uniformly/predictably.  By logging the ADC's harvest (say 8 sequence capture) it is quite simple to determine the ADC's "Acquisition Time Sequence" and the ADC's accuracy.   Much is revealed via such disciplined test.

Using a "dirty generator" - on the other hand - proves what?  (some - not moi - may suggest this camouflages errors.  Recall I'm simple reporter - conclusion left for others)

[/quote]

Ok, I missed "linear ramp".

No hard feelings, but sometimes your English is quite difficult for a non native English reader.

Regards

PAk said:

I need more power than M0 (of course a multiprocessor would do it)

Of course - we all recognized/knew that!

My post suggested a small, near cost-free - add on M0 to your MCU listed here!

You've overloaded your MCUs analog usage - thus a more capable part or, "divide & conquer."  My suggestion is the lowest cost means to meet your spec - and maintain your existing code effort...  Or - the earlier mention of external ADC - superior to those "kludged into" any MCU - may well reveal ADCs with the exact capability you seek.

MCU as kitchen sink - always supported w/out question here (but for an experienced few) - is not always, "best/brightest!"

PAk said:

sometimes your English is quite difficult for a non native English reader.

Blame/credit UCLA law for that.

You may find me somewhat responsive - simple, "request for restatement/clarification" most always works - don't you agree?  But when readers "struggle in silence" - that's not my fault.  How simply should I write - what is the standard?

Note that I participate here in brief/frantic "touch typed" blasts - usually when I'm stuck on one of our firm's tech/mkt/legal issues and need diversion. 

Overall I do take pains - write here much as I would for contracts - sometimes that world overflows...  Trust that more good than harm results - that is always my objective.   (and more than a few here regularly register their appreciation...)

cb1- said:

You may find me somewhat responsive - simple, "request for restatement/clarification" most always works - don't you agree?  But when readers "struggle in silence" - that's not my fault.  How simply should I write - what is the standard?

 Hi CB1, I fear your expressive writing can be difficult to some native too, and first time your writing was very hard to me understanding no more than 30%, time to time I got acquainted. Again I like read this level can help me grow language learning.

 I am also loosing my native language due to inability read write in advanced languages from mass, if I use a language level near your none understand me (is usable register also in English?) :(  so I prefer think in English as much as possible and read high level text.

 Post correction [I need read twice after correction before to post :(] <:)

cb1- said:

I vote - once more - for a properly designed/spec'ed linear ramp as "best for this ADC analysis!"  The linear ramp enables your easy prediction of exactly what measure the ADC should capture - at very predictable (i.e. "linear" points in time!)   All other methods - in our investigations - fall short...

 Hi CB1, I got just there to do some cleaning:

 Linear ramp seem the best one to test a converter, is appear as first degree than a sine but this is true just when it is far far away from Nyquist frequency.

 A so quite simple and slow change reveal a worst spectrum imprinting requiring a 100 or better 1000 time the fundamental bandwidth to avoid mask non linearity error with lack of bandwidth. Don't be fooled by linear in time so the better is a PURE sine but also this can be used good to evaluate THD and other parameter too. Triangular is a heavy test to amplifier and ADC too and linear nature may be just in phase delay or not depending from SH. Noise of a generator must be measured with instrument like Spectrum analyzer, on ADC side noise floor is the dominant paraeter and obtain noise floor low in a uC is not a simple thing, sometime also require tune or insert some (useless) part of code to patch digital noise.

 On first post my note was not an appointment to Amit work still better in midst of what still happen here but just missed PAk was probably trying acquire  I Q  working on ADC phase shift on single channel.

@Roberto,

I agree - many/most of your points.

But - consider that MCU ADC (again - any maker) is not exactly (yet) a, "Gold standard!"  Note that years past this vendor acquired famed analog house "BB" - those were/are real/proper analog devices.

Indeed a "pure" (not dirty) sine-wave achieves much - but not (imho) as a first-order test.  Simple, low freq linear ramp - as I've introduced here - will clarify accuracy, time step precision, and linearity of ADC.  So very hard to achieve any of those via sine signal - and far more expensive.

Recall cb1's long/on-going plea to, "raise the use/prominence of KISS!"  Sine is fine - "after one learns the inherent weakness of MCU based ADC."  Armed with the knowledge gained via linear ramp - isn't it far easier to apply "correction factors/offsets" - which would be otherwise lost?   And then even sophisticated user wonders - "Why?"

Assume little - devise interlocked test mechanism - which may self-regulate.  (enable the test to "test itself" - as much as that is/becomes possible)  

cb1- said:

Recall cb1's long/on-going plea to, "raise the use/prominence of KISS!"  Sine is fine - "after one learns the inherent weakness of MCU based ADC."  Armed with the knowledge gained via linear ramp - isn't it far easier to apply "correction factors/offsets" - which would be otherwise lost?   And then even sophisticated user wonders - "Why?"

 Hi CB1, this is a dangerous terrain to be sure have foot on solid rock than sliding sand....

 ADC is an intermixed (from mixed signals) analog and digital part so it is also an intermixed chaos of S domain and Z domain both behaving bad parameter and response.

 In this way can a linear signal both be distorted and or delayed (from SH input) then this infer again on ADC precision and using a so nervous wave yes reveal a lot of trouble but need a more and more deep knowledge missing from mean user also if "middle advanced" one.

 So it is a pleasure exchange experience but sometimes a strong lab test is needed to reveal where this can be weak or strong. I reserve go to lab to do some confidence test and then see what happen. Remember a 20MHz pure sine generator cannot deliver more than 10KHz triangular, Agilent 20MHz triangular generator has an end stage of more than 2GHz bandwidth seems more a microwave fixture than a low frequency generator.  Recent technology improved things and cost but I still prefer relay on secure source of data. From low cost function generator I measured triangular wave after 1MHz and forever is not a triangle, scope was an analog 450MHz PWT TEK or 2GSPS  Agilent, In this case I forever prefer analog to Digital.