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DMA: Bit in register BERFLAG is not set cause of "DMA imprecise read/write error"

oliver.gruendonner
Intellectual 830 points
Other Parts Discussed in Thread: TMS570LS3137

Hi.

My question is regarding the TMS570LS3137.

In spns162b.pdf, page 96 are also the following two ESM channel assignments stated:
  * DMA/DMM - imprecise read error, Group1, channel 5
  * DMA/DMM - imprecise write error, Group1, channel 13
I generate the DMA imprecise read error, by a DMA-read access from an unimplemented address (using DMA channel 4). I observe that the bit 5 in the ESM register ESMSR1 (i.e. ESMSR1.5) will be set to 1. BUT I cannot observe that the bit 4 in the DMA register BERFLAG (i.e. BERFLAG.4) will be set (Reason why bit 4: Since DMA channel 4 is used.).
I generate the DMA imprecise write error, by a DMA-write access to an unimplemented address (using DMA channel 5). I observe that the bit 13 in the ESM register ESMSR1 (i.e. ESMSR1.13) will be set to 1. BUT I cannot observe that the bit 5 in the DMA register BERFLAG (i.e. BERFLAG.5) will be set (Reason why bit 5: Since DMA channel 5 is used.).

Several notes:
  * Note 1: I've tried it with DMA interrupts enabled and disabled, i.e.:
      - GCHIENAS.4 = GCHIENAS.5 = 1
      - GCHIENAS.4 = GCHIENAS.5 = 0
     But I observed no difference.
  * Note 2: DMA register BERMAP = 0.
  * Note 3: In case a DMA - MPU error will be generated (i.e. ESM channel "DMA - MPU", Group1, channel 2), I observe the following:
      - The bit 2 in the ESM register ESMSR1 (i.e. ESMSR1.2) will be set to 1.
      - The corresponding bit in DMA register BERFLAG will also be set to 1.

So my question is: Why will the corresponding bits in DMA register BERFLAG not be set in case of a DMA - imprecise read/write error?

Regards
Oliver.

  • 0
    TI__Guru**** 190876 points

    Hello Oliver,

      Assertion of ESM GP1.5 or GP1.13 is not generated by the DMA or the DMM but rather from an Infrastructure component in the device. The buffering inside the infrastructure component causes the imprecise error response behavior. The way the bus error such as an illegal address is handled specifically for DMA and DMM is by directly routing the error to the ESM GP1.5 or GP1.13. The DMA will not receive any bus error response. It always thinks there is no bus error coming from the slaves. This means the BERFLAG will not be set due to imprecise read/write errors.