• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 29 subscribers
  • Views 1579 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EK-TM4C1294XL PWM0 GEN0, No PWM output GPIO PF0/PF1

Genatco
Guru 55913 points
Other Parts Discussed in Thread: LM3S8971

PWM0-GEN1 GPIO- PF2/PF3  and PWM-GEN2 GPIO  PG0/PG1 a PWM output control block signals only on the high side. Moved Ethernet EN0LED0/2 board LED 3/4 to GPIO PK4/5 long ago freeing up GEN0/1 for PWM use. Seemed odd anyone would have purposefully removed access to PWM0 GEN0 without disclosing a reason why before purchasing the Launch Pad.

Believe I have been bamboozled by AKA experimental chip. Not an Launch Pad advocate by choice rather by force of an NDNA Stellaris chip the LM3S8971 which BTW has none of these bizarre issues. Sadly the Stellaris chip was barely out of the starting gate when it got hood winked, sidelined and moth balled for what ever reasons.

Were Ethernet link and activity LED3/4 placed on PWM0 GEN0 GPIO PF0/1 intentionally to cover up chip flaws, seemingly so would be my belief. Booster Pack headers 1 & 2 have omitted PWM0 GEN0 PF0 possibly for the very same reason. 

Errata document states PWM0 may not trigger ADC or PWM interrupts. That is an understatement - "GEN0 will not do either what so ever", should be added to the errata document.

  • 0
    Guru 47900 points

    So - uh - wanna tell us how you really feel?

    (for those counting/tabulating - log this as 2nd use of, "bamboozled" - both by this {tres diplomatique} poster...)

    Feel your pain buddy - will try to help via "C - channel."  (first I've heard this loss of Gen0 - bet you I can fix...)

    *** new conversation launched - this issue...

  • 0 in reply to cb1
    Guru 55913 points

    1805.Tiva TM4C1294X Errata rev1-3.pdf

    Don't get me wrong a primary objective of any MPU is to find way onto many boards as possible.

    Yet such a condition PWM0 GEN0 not to generate interrupts is one thing but for it to become Helen Keller impaired is quite the embarrassment. This chip should never have been put into any production as dysfunctional several areas are within. This is why insurance contracts are taken out on works of art, pricy cars and  jewelry. Has not TI ever considered to insure their processes against Mayhem? ALState claims they can help anyone avoid the damages of Mayhem why not an IC chip, doesn't he deserve like protection from would be causes of Mayhem?

     

  • 0 in reply to Genatco
    Guru 117855 points

    And there are those (unkind) who challenge my (occasional/well earned) release from, "ment ward/home."

    One doubts the silica mass much: cares/feels/dreams  re: sales success. 

    And might, "MCU" better describe this offending, "object of your affection."   (yet we indeed, "feel your pain...")

  • 0 in reply to cb1_mobile
    Guru 55913 points

    Has become quite clear the objective was to decoy any such use of PWM0 GEN0 so sacrificed for EN0/1 LEDS drives. Not to forget other defects encountered fore mentioned. Errata disclosure is intended to protect the public from known issues that might otherwise do harm unto them while in they are in the discovery process. Here that objective has miserably lost the edge to perform such duty.

    My company has suffered, compromised in collateral damages both the NDNA of the LM3S9871 and now this set back. Not forgone LMI besieged take over and moth balling the BLDC-RDK a good product which the only fault required extensive code debugging, something TI is very good at. The LM3S8971 at least functions on all PWM0 generators Boot Loader and all where the TM4C1294 has simply left the building just as LMI did.

    << Team TI can turn this 120Mhz road runner around >>

  • 0 in reply to Genatco
    Guru 55913 points

    PWM0 GEN3 outputs 6/7 appear functional and can be used in place of dysfunctional GEN0 -0/1 outputs. Not forgoing once again EN0-LED0/2 trace rerouting GPIO PK4/5 over to PF0/1.

    Seemingly a work around for the very dead outputs of GEN0-0/1. Oddly open loop commutation Halls sequencing is not driving the high side outputs of any generator while in slow decay. That forced in sensorless operation being a likely code failure suspect.

    Not exactly sure of that yet however staying the course for now, will retract few earlier statements above.

  • 0 in reply to Genatco
    Guru 117855 points

    Good for you - perhaps you'd care to share/credit "just how" that "workaround" use of PWM0Gen4 dawned?  

    Diagnosis - issue resolution - delivered, (once again) as promised...

    Moving to today's (latest) protest/complaint, Brett, "Halls sequencing is not driving the high side outputs of any generator while in slow decay."  In our 5+ years successful use of, "spun-off/enhanced/extended RDK-BLDC" we've never (not even once) been able to, "not PWM drive" the high-side gate-drivers and mated FETs!  What have you changed - what have you done to "break" that (past) robust vendor code?

    Might, "few" earlier statement retraction be slight understatement?  (i.e. what is the meaning of "few" - or presidential, "is"?)

  • 0 in reply to cb1_mobile
    Guru 55913 points

    "Halls sequencing is not driving the high side outputs of any generator while in slow decay." 

    Inferring opposites FET modulate high side in slow decay FOC open loop commutation sequence [5,1,3,2,6,4] (dead band protection turned on), PWM0 - 6 MCU outputs. Recall seeing activity both low & high side during slow decay in past all 3 gate driver inputs.

    That scenario, would not the high side all stay on during open loop commutation sequencing, surely smoke N channel FET if not provided a modulated gate drive.

    Fast decay mode; open loop commutation no signal activity noticed on any of 6 outputs, all stay low. Totally at a loss what is happening. ADC requires tweak last fired phase A/B/C shift left 2 bits after adding physical generator 4. GEN 0=1 , 2=3, 3=4 makes for most confusing not starting from GEN0.

     

  • 0 in reply to Genatco
    Guru 47900 points

    Believe that you can confirm that far past - and into today - I've been able to provide generally effective, BLDC SW guidance. 

    I'd prefer to escape this, "Bamboozled-centric" thread - and suspect that a fresh post identifying your "present" BLDC issues (so titled - so much the better) - would be more, "topic appropriate."  (and if you know me - correctness of topic registers brightly - my firm's radar...)

  • 0 in reply to cb1
    Guru 55913 points

    War wounds self inflicted played part of such demise in no signals emerging from PWM control block during fast decay mode and only low side signals operation during slow decay.

    For anyone else lower down the food chain the oscilloscope wave trace reveal slow and fast decay both PWM low and high side drivers with one slight difference. Slow decay high side drives have far fewer yet some random PWM activity inside the minimum pulse width signal while the low side modulates quite extensively. Fast decay signals low/high PWM remarkably identical.

    My friend on Wicked Tuna Pin Wheel boat would say for high side slow decay, this is "BOOST".