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VCLKA4 Setup for RM48 HDK

Hector_Tortosa
Intellectual 475 points
Other Parts Discussed in Thread: HALCOGEN, DP83640, RM48L952

Hi Everyone,

I have some questions about the HDK Clock configuration, so I want it to be running at 220Mhz with lwIP.

1- According to the specs, the phy needs to be running at 50Mhz, provided by an external clock. This has been already implemented in the HDK, so I shall not worry about this.

2-The VCLKA4 for the EMAC needs to be configured at 40Mhz according to:http://processors.wiki.ti.com/index.php/HALCoGen_Ethernet_Driver_and_lwIP_Integration_Demonstration

3-Why? Is this a requierement? Where? Can It be running a different speed? 

I tried to find any reference in the technical documents of the RM48 but anywhere says that needs to be 40Mhz.

In fact they say that the maximum speed must be 50Mhz. 

4-Does this mean that I can but a speed between 40Mhz and 50Mhz?

Thanks.

  • 0
    TI__Mastermind 49120 points

    Hi Victor,

    The main purpose of providing this VCLKA4 was to avoid having a second clock source on the PCB for the Ethernet PHY. You can generate the required 25MHz  or 50MHz clock signal on VCLKA4 and then send it to the PHY via the ECLK pin. One of the clock test mode configurations allows you to output VCLKA4 onto the ECLK pin. Configure CLKTEST[3:0] = 1110b.

    If you are running the main HCLK/GCLK clock domains at 220MHz, then it is necessary for you to use the second PLL to output a 50MHz signal so that it can be used as the clock source for VCLKA4.

    I will find out the reason behind specifying a 40MHz requirement on VCLKA4 on the wiki page and get back to you. My guess is that since they have programmed both PLL outputs to 160MHz, and since VCLKA4(max) is 50MHz, the only choice left with this PLL configuration is 40MHz.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 475 points

    Hi Sunil,


    Thank you for your reply,

    I see that there is a external clock which produces the RMII_MHZ_50, this one goes to the DP83640 giving the 50Hz.

    But in other hand we have the VLCKA4 which provides the frequency to the EMAC Driver.

    Right know I have it working with 220MHz and 44MHz on the EMAC. At least im getting IP from the DHCP. Its 50Mhz a fixed value or can be a value up to 50Mhz.


    Following the technical document rm48l550 from Texas Instruments says in the page 47 that the  fVCLKA4 have a maximum of 50Mhz, does this means that can run a bit slower.

    If this can't be and has to run to a certain speed, which frequency should be for the RM48L952ZWT (Max Speed 220MHz) 55 Hz? If I put PLL1 to 220, then if I put a divider of 4 I would get 55Mhz (Which is more than the Maximun).

    Thanks for your reply.

  • 0 in reply to Hector_Tortosa
    TI__Mastermind 49120 points

    Hi Victor,

    Since the HDK already has a separate dedicated clock source for the DP you do not need to configure anything with respect to VCLKA4. That is, this clock signal is not used anywhere and its frequency does not matter. Also, do not configure the I/O multiplexors to select the MII_TX_AVCLK4 and MII_RX_AVCLK4 functionality.

    The EMAC IP inside the RM48x MCU uses the VCLK3 clock domain. This is divided down from HCLK and can be as fast as 110MHz for RM48L952.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 475 points

    Hi Sunil.

    Thats correct, VLCKA4 disabled in the HDK and the EMAC keeps working correcly.

    Allow me to ask you one more thing about clocks.

    Can VCLK1..2..3 run at the maximum speed (220MHZ) selecting 0 as divider? Or the minimum divider is 1?

    Thanlks.