TMS570LC4357 DMA MPU vs. DMA NMPU

Hi Libo,

  My asnwers are inline.

1. Table 4-1 in the TRM summarizes the "Bus Master/Slave Connectivity for Peripheral Interconnect Subsystem". If an access is not allowed in this table, this means, such access is disabled at hardware level (I assume there is no hardware connection in such case).  So this table is the starting point of all bus master ID filtering configuration. In other words, we can only configure the register like PS0MSTID_L to disable an access which is allowed in the table, but we can't enable an access which is disallowed in the table. For example,  we can clear PS0MSTID_L[9] to disable the access from DAP to MibSPI5. But we can't set PS0MSTID_L[3] to 1 to enable the access from HTU1 to MibSPI5. Or more exactly, it doesn't matter if PS0MSTID_L[3] is set to 1 or 0 since such access is disabled at hardware level already. Is this understanding correct?

CT>> Your understanding is correct. The Peripheral Interconnect Subsystem is a partial crossbar. It will be an illegal address for the HTU1 to acess MibSPI5.

2. In the same table, HTU1 is not allowed to access PCR3. But HTU RAMs are under PCR3 (PCS[38, 39]). Is it here a typo?

CT>> It is not a typo. HTU RAMs are private memory to the HTU modules. HTU modules do not need to go through the peripheral interconnect subsystem to access its local memory.

3. DAP has access to almost all peripherals. If we don't use DAP, is it OK to disable all accesses from DAP to the peripherals? What is the suggestion from TI?

CT>> DAP is a container module. One of DAP's components is the  AHB-AP which is the master port that can be used by the debugger to access the system resources. I will suggest not to disable DAP AHB-AP from accessing the system resoures.

4. Section 2.5.3.5 of the TRM mentions "quadrant" . It seems that a quadrant is 1/4 of a frame, and a frame is always 1KB. Right?

CT>> If you are talking  about the Peripheral Protection Set Register in section 2.5.3.5 then the answer is yes. The granularity of each Peripheral Select is 1k and each quadrant will be 256 bytes.  Please note that this is not the masterID checking that I referred to. If you are interested to implement masterID filtering then please refer to sections starting at 2.5.3.28 to 2.5.3.40. The masterID checking is a new feature added for LC43xx.

5. In Tab. 2-15, PS[31:30]  are used to select both Ethernet Slave under PCR2 and PCR3 registers. Similarly, PPSE[4, 5, 6] are double mapped to select PCR1 /PCR2 register,PS_SCR_S NMPU and CPGMAC NMPU. Is this correct?

CT>> Libo, could you please download the latest TRM. The latest TRM Table 2-15 is the DCC1 mapping. I think you are refering to Table 2-2 in the latest TRM, right? There are three PCRs in LC4357. Each PCR can decode its own PS, PCS, PPS and PPSE frames. The PPSE[4,5,6] decoded by the PCR2 is to select PCR2 registers and NMPU for CPGMAC. When I said PCR2 registers I refer to PCR2 module's internal registers. The PPSE[4,5,6] decoded by the PCR1 module is used to select PCR1's internal registers, and NMPU for PS_SCR_S and NMPU for DMA PortA.

6. Since DMA NMPU applies only to access to SCR, bus master filtering only applies to access to PCR, and the built-in MPU applies to accesses to both SCR and PCR, it seems that the built-in MPU is most effective if we want to implement only the basic memory protection mechanism.  Or there is some other more preferred way to set up memory protection?

CT>> Our safety diagnostic strategy for LC43xx is to provide a maximum of two levels of MPU protection from a master to a slave. But it is your system decision if you want to use two levels or one will suffice.

Hi Libo,

  Thanks for bringing to our attention the mistake in TRM. You are right that it should be PS[7-0]QUAD[3-0] instead of PCS[7-0]QUAD[3-0]. I will file a documentation update for this.

  If you look at the PCR3 PS[0] in Table 2-2, it is the MibSPI5. The MibSPI5 occupies the lower 2 quadrants. The upper two quadrandts are not implemented since there are no modules mapped to the upper quadrants of PS[0]. This is the reason that the PS0MSID_H for PCR3 is all zeros. Since the MibSPI5 occupies 2 quadrants, it is only necessary to enable/disable masterID using the quadrant 0 rather than both quadrant 0 and 1. This is the reason the upper 16 bits of the PS0MSTID_L is zero.

  MibSPI3 is mapped to the lower 2 quadrants of the PS[1] and MibSPI4 is mapped to the upper 2 quadrants of the PS[1]. Again, since each MibSPI occupies two quadrants, it is necessary to only enable/disable using the lower quadrant of the occupied 2 quadrants of each module. This is why it is showing 0x0000FFFF for PS1MSID_L and PS2MSID_H.

Hi Libo,

  PPCs, PPSE and PPS are the chip selects for the system peripherals and system peripheral memories. There are no protection registers like PPROTSETx for these type of chip selects. Most of the system peripheral registers are only accessible in privilege mode. However, there may be some exception. You will need to go to each module register to find out if a specific bit is privilege protected or not. For example, in the SYS module, the SYSPCx registers are not privilege protected. The PMPROTSETx and PPROTSETx are for user peripherals and user peripheral memories.

Hi Libo,

  Let me break up your paragraph into multiple questions.

thanks for the explanation. Some registers in user peripheral are privilege protected. For such registers, the corresponding PPROTSETx or PMPROTSETx register configuration has no effect, right?

CT>> There is a slight difference. Let's say the PPROTSETx is not set and you write to a privilege protected register in a module in user mode, the outcome is that the write is ignored and there is no bus error (abort to the CPU) generated by the slave module. However, if you set the PPROSETx then a CPU access in user mode to any register in the module will be blocked by the PCR. The slave module does not even see the access. The PCR will generate the bus error (which becomes an abort to the CPU).

This implies that we can only add more access restriction to a register but can not reduce the restriction. For example, PS[2] of PCR3 selects MibSPI1. PPROTSET0[11:8] is used to configure if the MibSPI1 registers can be accessed only in privileged mode or also in user mode.

CT>> Yes. The PPROTSETx protects at a quadrant level. Violations is directly handled by the PCR in terms of bus errors back to the master.

Since MibSPI1 registers occupy less than 512 byte, only PPROTSET[8] is implemented. If a MibSPI1 register can be accessed in user mode by default, then it can only  be accessed in privileged mode if PPROTSET[8] is set to 1. Is my understanding correct?

CT>> Yes. the understanding is correct. Only PPROTSET[8] is needed to enable/disable protection for MibSPI1. PPROTSET[9] is not needed.

Hi Libo,

  I should have mentioned that L2RAMW is an exception to the behavior I tried to generalize for other modules. L2RAMW is a new module for LC4357.  It deviates a bit from other modules in terms of error handling. This module will generate bus error for illegal access for privilege protected registers. It will also generate bus error for accessing unimplemented register space (illegal address).

  I will suggest to open a new thread for new topics. This will be easier for the community members to find the relevant questions and answers.