• State Resolved
  • Locked Locked
  • Replies 16 replies
  • Subscribers 31 subscribers
  • Views 2079 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LC4357 PCR1 register values in CCS 5.5

Libo Luo
Intellectual 940 points
Other Parts Discussed in Thread: TMS570LC4357, TMS570LS3137, RM57L843

Hi CCS team,

I use CCS 5.5 to debug design based on TMS570LC4357. I have noticed that the register values of PCR1 register PPSExMstID_L and PPSExMstID_H (x=0..7) are swapped in the register view.

The default values for PPSE0MstID_L and PPSE0MstID_H are 0x0000_FFFF and 0x0000_0000 respectively. The values in memory browser are correct. The values in register view are swapped: PPSE0MstID_L is 0x0000_0000 and PPSE0MstID_H is 0x0000_FFFF. I haven't checked if this is fixed in CCS 6.0.

Please check this.

Thanks and regards,

Libo

  • 0
    TI__Guru 68920 points

    Libo,


    I'll look into this and confirm one way or the other.   Thanks for the report.

  • 0 in reply to Anthony F. Seely
    TI__Mastermind 22715 points

    Libo,

    would you please take a look at the values at the physical address in the CCS memory window? This will help us determine if it is just a CCS device xml file (where all the registers are defined for CCS) issue.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Anthony F. Seely
    TI__Guru 68920 points

    Libo,

    The files that come with CCS6.0 now are the official released support files for the LC4357.

    I think you probably have an advanced copy and your xml file is probably named with a version 5.3.0.

    CCC6.0 has the correct version for the module (5.5.0) and there are many differences in the XMLs not just this one register.   However, I can confirm that in 5.3.0 there was an error and it matches what you describe,  instead of  PPSE0MstID_L pointing to offset 0x440 it is pointing to 0x444 and many other register addresses are shifted.

    For your information below is the diff -- you can see how extensive and I would use this as a reason to migrate to CCS6.0.   Also there are other fixes related to flash programming that are available in version 6.0 - it's just more polished with the LC4357 than the advanced copy that you're using.

    diff --git a/ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.3.0.xml b/ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.5.0.xml
    similarity index 87%
    rename from ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.3.0.xml
    rename to ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.5.0.xml
    index 7b0d284..2166175 100644
    --- a/ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.3.0.xml
    +++ b/ccs_base/common/targetdb/Modules/hercules/hercules_pcr_spec_5.5.0.xml
    @@ -1,4 +1,4 @@
    -<?xml version="1.0" encoding="utf-8"?>
    +<?xml version="1.0" encoding="utf-8"?>
     <module id="Pcr" HW_revision="" XML_version="1" description="">
       <!-- (c) Texas Instruments 2003-2012, All rights reserved. -->
       <!-- Filename:Hercules_PCR_5.3.0.xml                           -->
    @@ -112,108 +112,109 @@
       <register id="PPS6MstId_H" acronym="PPS6MstId_H" offset="0x434" width="32" description="Privileged Peripheral Frame 6 (Quadrant 2 and 3) MasteriD Protection Register"></register>
       <register id="PPS7MstId_L" acronym="PPS7MstId_L" offset="0x438" width="32" description="Privileged Peripheral Frame 7 (Quadrant 0 and 1) MasteriD Protection Register"></register>
       <register id="PPS7MstId_H" acronym="PPS7MstId_H" offset="0x43C" width="32" description="Privileged Peripheral Frame 7 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE0MstId_L" acronym="PPSE0MstId_L" offset="0x444" width="32" description="Privileged Peripheral Extended Frame 0 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE0MstId_H" acronym="PPSE0MstId_H" offset="0x448" width="32" description="Privileged Peripheral Extended Frame 0 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE1MstId_L" acronym="PPSE1MstId_L" offset="0x44C" width="32" description="Privileged Peripheral Extended Frame 1 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE1MstId_H" acronym="PPSE1MstId_H" offset="0x450" width="32" description="Privileged Peripheral Extended Frame 1 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE2MstId_L" acronym="PPSE2MstId_L" offset="0x454" width="32" description="Privileged Peripheral Extended Frame 2 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE2MstId_H" acronym="PPSE2MstId_H" offset="0x458" width="32" description="Privileged Peripheral Extended Frame 2 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE3MstId_L" acronym="PPSE3MstId_L" offset="0x45C" width="32" description="Privileged Peripheral Extended Frame 3 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE3MstId_H" acronym="PPSE3MstId_H" offset="0x460" width="32" description="Privileged Peripheral Extended Frame 3 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE4MstId_L" acronym="PPSE4MstId_L" offset="0x464" width="32" description="Privileged Peripheral Extended Frame 4 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE4MstId_H" acronym="PPSE4MstId_H" offset="0x468" width="32" description="Privileged Peripheral Extended Frame 4 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE5MstId_L" acronym="PPSE5MstId_L" offset="0x46C" width="32" description="Privileged Peripheral Extended Frame 5 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE5MstId_H" acronym="PPSE5MstId_H" offset="0x470" width="32" description="Privileged Peripheral Extended Frame 5 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE6MstId_L" acronym="PPSE6MstId_L" offset="0x474" width="32" description="Privileged Peripheral Extended Frame 6 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE6MstId_H" acronym="PPSE6MstId_H" offset="0x478" width="32" description="Privileged Peripheral Extended Frame 6 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE7MstId_L" acronym="PPSE7MstId_L" offset="0x47C" width="32" description="Privileged Peripheral Extended Frame 7 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE7MstId_H" acronym="PPSE7MstId_H" offset="0x480" width="32" description="Privileged Peripheral Extended Frame 7 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE8MstId_L" acronym="PPSE8MstId_L" offset="0x484" width="32" description="Privileged Peripheral Extended Frame 8 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE8MstId_H" acronym="PPSE8MstId_H" offset="0x488" width="32" description="Privileged Peripheral Extended Frame 8 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE9MstId_L" acronym="PPSE9MstId_L" offset="0x48C" width="32" description="Privileged Peripheral Extended Frame 9 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE9MstId_H" acronym="PPSE9MstId_H" offset="0x490" width="32" description="Privileged Peripheral Extended Frame 9 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE10MstId_L" acronym="PPSE10MstId_L" offset="0x494" width="32" description="Privileged Peripheral Extended Frame 10 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE10MstId_H" acronym="PPSE10MstId_H" offset="0x498" width="32" description="Privileged Peripheral Extended Frame 10 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE11MstId_L" acronym="PPSE11MstId_L" offset="0x49C" width="32" description="Privileged Peripheral Extended Frame 11 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE11MstId_H" acronym="PPSE11MstId_H" offset="0x4A0" width="32" description="Privileged Peripheral Extended Frame 11 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE12MstId_L" acronym="PPSE12MstId_L" offset="0x4A4" width="32" description="Privileged Peripheral Extended Frame 12 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE12MstId_H" acronym="PPSE12MstId_H" offset="0x4A8" width="32" description="Privileged Peripheral Extended Frame 12 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE13MstId_L" acronym="PPSE13MstId_L" offset="0x4AC" width="32" description="Privileged Peripheral Extended Frame 13 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE13MstId_H" acronym="PPSE13MstId_H" offset="0x4B0" width="32" description="Privileged Peripheral Extended Frame 13 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE14MstId_L" acronym="PPSE14MstId_L" offset="0x4B4" width="32" description="Privileged Peripheral Extended Frame 14 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE14MstId_H" acronym="PPSE14MstId_H" offset="0x4B8" width="32" description="Privileged Peripheral Extended Frame 14 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE15MstId_L" acronym="PPSE15MstId_L" offset="0x4BC" width="32" description="Privileged Peripheral Extended Frame 15 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE15MstId_H" acronym="PPSE15MstId_H" offset="0x4C0" width="32" description="Privileged Peripheral Extended Frame 15 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE16MstId_L" acronym="PPSE16MstId_L" offset="0x4C4" width="32" description="Privileged Peripheral Extended Frame 16 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE16MstId_H" acronym="PPSE16MstId_H" offset="0x4C8" width="32" description="Privileged Peripheral Extended Frame 16 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE17MstId_L" acronym="PPSE17MstId_L" offset="0x4CC" width="32" description="Privileged Peripheral Extended Frame 17 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE17MstId_H" acronym="PPSE17MstId_H" offset="0x4D0" width="32" description="Privileged Peripheral Extended Frame 17 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE18MstId_L" acronym="PPSE18MstId_L" offset="0x4D4" width="32" description="Privileged Peripheral Extended Frame 18 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE18MstId_H" acronym="PPSE18MstId_H" offset="0x4D8" width="32" description="Privileged Peripheral Extended Frame 18 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE19MstId_L" acronym="PPSE19MstId_L" offset="0x4DC" width="32" description="Privileged Peripheral Extended Frame 19 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE19MstId_H" acronym="PPSE19MstId_H" offset="0x4E0" width="32" description="Privileged Peripheral Extended Frame 19 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE20MstId_L" acronym="PPSE20MstId_L" offset="0x4E4" width="32" description="Privileged Peripheral Extended Frame 20 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE20MstId_H" acronym="PPSE20MstId_H" offset="0x4E8" width="32" description="Privileged Peripheral Extended Frame 20 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE21MstId_L" acronym="PPSE21MstId_L" offset="0x4EC" width="32" description="Privileged Peripheral Extended Frame 21 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE21MstId_H" acronym="PPSE21MstId_H" offset="0x4F0" width="32" description="Privileged Peripheral Extended Frame 21 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE22MstId_L" acronym="PPSE22MstId_L" offset="0x4F4" width="32" description="Privileged Peripheral Extended Frame 22 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE22MstId_H" acronym="PPSE22MstId_H" offset="0x4F8" width="32" description="Privileged Peripheral Extended Frame 22 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE23MstId_L" acronym="PPSE23MstId_L" offset="0x4FC" width="32" description="Privileged Peripheral Extended Frame 23 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE23MstId_H" acronym="PPSE23MstId_H" offset="0x500" width="32" description="Privileged Peripheral Extended Frame 23 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE24MstId_L" acronym="PPSE24MstId_L" offset="0x504" width="32" description="Privileged Peripheral Extended Frame 24 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE24MstId_H" acronym="PPSE24MstId_H" offset="0x508" width="32" description="Privileged Peripheral Extended Frame 24 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE25MstId_L" acronym="PPSE25MstId_L" offset="0x50C" width="32" description="Privileged Peripheral Extended Frame 25 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE25MstId_H" acronym="PPSE25MstId_H" offset="0x510" width="32" description="Privileged Peripheral Extended Frame 25 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE26MstId_L" acronym="PPSE26MstId_L" offset="0x514" width="32" description="Privileged Peripheral Extended Frame 26 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE26MstId_H" acronym="PPSE26MstId_H" offset="0x518" width="32" description="Privileged Peripheral Extended Frame 26 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE27MstId_L" acronym="PPSE27MstId_L" offset="0x51C" width="32" description="Privileged Peripheral Extended Frame 27 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE27MstId_H" acronym="PPSE27MstId_H" offset="0x520" width="32" description="Privileged Peripheral Extended Frame 27 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE28MstId_L" acronym="PPSE28MstId_L" offset="0x524" width="32" description="Privileged Peripheral Extended Frame 28 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE28MstId_H" acronym="PPSE28MstId_H" offset="0x528" width="32" description="Privileged Peripheral Extended Frame 28 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE29MstId_L" acronym="PPSE29MstId_L" offset="0x52C" width="32" description="Privileged Peripheral Extended Frame 29 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE29MstId_H" acronym="PPSE29MstId_H" offset="0x530" width="32" description="Privileged Peripheral Extended Frame 29 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE30MstId_L" acronym="PPSE30MstId_L" offset="0x534" width="32" description="Privileged Peripheral Extended Frame 30 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE30MstId_H" acronym="PPSE30MstId_H" offset="0x538" width="32" description="Privileged Peripheral Extended Frame 30 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PPSE31MstId_L" acronym="PPSE31MstId_L" offset="0x53C" width="32" description="Privileged Peripheral Extended Frame 31 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    -  <register id="PPSE31MstId_H" acronym="PPSE31MstId_H" offset="0x540" width="32" description="Privileged Peripheral Extended Frame 31 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    -  <register id="PCS0MstId" acronym="PCS0MstId" offset="0x544" width="32" description="Memory Frame  0 MasteriD Protection Register"></register>
    -  <register id="PCS2MstId" acronym="PCS2MstId" offset="0x548" width="32" description="Memory Frame  2 MasteriD Protection Register"></register>
    -  <register id="PCS4MstId" acronym="PCS4MstId" offset="0x54C" width="32" description="Memory Frame  4 MasteriD Protection Register"></register>
    -  <register id="PCS6MstId" acronym="PCS6MstId" offset="0x550" width="32" description="Memory Frame  6 MasteriD Protection Register"></register>
    -  <register id="PCS8MstId" acronym="PCS8MstId" offset="0x554" width="32" description="Memory Frame  8 MasteriD Protection Register"></register>
    -  <register id="PCS10MstId" acronym="PCS10MstId" offset="0x558" width="32" description="Memory Frame  10 MasteriD Protection Register"></register>
    -  <register id="PCS12MstId" acronym="PCS12MstId" offset="0x55C" width="32" description="Memory Frame  12 MasteriD Protection Register"></register>
    -  <register id="PCS14MstId" acronym="PCS14MstId" offset="0x560" width="32" description="Memory Frame  14 MasteriD Protection Register"></register>
    -  <register id="PCS16MstId" acronym="PCS16MstId" offset="0x564" width="32" description="Memory Frame  16 MasteriD Protection Register"></register>
    -  <register id="PCS18MstId" acronym="PCS18MstId" offset="0x568" width="32" description="Memory Frame  18 MasteriD Protection Register"></register>
    -  <register id="PCS20MstId" acronym="PCS20MstId" offset="0x56C" width="32" description="Memory Frame  20 MasteriD Protection Register"></register>
    -  <register id="PCS22MstId" acronym="PCS22MstId" offset="0x570" width="32" description="Memory Frame  22 MasteriD Protection Register"></register>
    -  <register id="PCS24MstId" acronym="PCS24MstId" offset="0x574" width="32" description="Memory Frame  24 MasteriD Protection Register"></register>
    -  <register id="PCS26MstId" acronym="PCS26MstId" offset="0x578" width="32" description="Memory Frame  26 MasteriD Protection Register"></register>
    -  <register id="PCS28MstId" acronym="PCS28MstId" offset="0x57C" width="32" description="Memory Frame  28 MasteriD Protection Register"></register>
    -  <register id="PCS30MstId" acronym="PCS30MstId" offset="0x580" width="32" description="Memory Frame  30 MasteriD Protection Register"></register>
    -  <register id="PCS32MstId" acronym="PCS32MstId" offset="0x584" width="32" description="Memory Frame  32 MasteriD Protection Register"></register>
    -  <register id="PCS34MstId" acronym="PCS34MstId" offset="0x588" width="32" description="Memory Frame  34 MasteriD Protection Register"></register>
    -  <register id="PCS36MstId" acronym="PCS36MstId" offset="0x58C" width="32" description="Memory Frame  36 MasteriD Protection Register"></register>
    -  <register id="PCS38MstId" acronym="PCS38MstId" offset="0x590" width="32" description="Memory Frame  38 MasteriD Protection Register"></register>
    -  <register id="PCS40MstId" acronym="PCS40MstId" offset="0x594" width="32" description="Memory Frame  40 MasteriD Protection Register"></register>
    -  <register id="PCS42MstId" acronym="PCS42MstId" offset="0x598" width="32" description="Memory Frame  42 MasteriD Protection Register"></register>
    -  <register id="PCS44MstId" acronym="PCS44MstId" offset="0x59C" width="32" description="Memory Frame  44 MasteriD Protection Register"></register>
    -  <register id="PCS46MstId" acronym="PCS46MstId" offset="0x5A0" width="32" description="Memory Frame  46 MasteriD Protection Register"></register>
    -  <register id="PCS48MstId" acronym="PCS48MstId" offset="0x5A4" width="32" description="Memory Frame  48 MasteriD Protection Register"></register>
    -  <register id="PCS50MstId" acronym="PCS50MstId" offset="0x5A8" width="32" description="Memory Frame  50 MasteriD Protection Register"></register>
    -  <register id="PCS52MstId" acronym="PCS52MstId" offset="0x5AC" width="32" description="Memory Frame  52 MasteriD Protection Register"></register>
    -  <register id="PCS54MstId" acronym="PCS54MstId" offset="0x5B0" width="32" description="Memory Frame  54 MasteriD Protection Register"></register>
    -  <register id="PCS56MstId" acronym="PCS56MstId" offset="0x5B4" width="32" description="Memory Frame  56 MasteriD Protection Register"></register>
    -  <register id="PCS58MstId" acronym="PCS58MstId" offset="0x5B8" width="32" description="Memory Frame  58 MasteriD Protection Register"></register>
    -  <register id="PCS60MstId" acronym="PCS60MstId" offset="0x5BC" width="32" description="Memory Frame  60 MasteriD Protection Register"></register>
    -  <register id="PCS62MstId" acronym="PCS62MstId" offset="0x5C0" width="32" description="Memory Frame  62 MasteriD Protection Register"></register>
    -  <register id="PPCS0MstId" acronym="PPCS0MstId" offset="0x5C4" width="32" description="Priviledged Memory Frame  0 MasteriD Protection Register"></register>
    -  <register id="PPCS2MstId" acronym="PPCS2MstId" offset="0x5C8" width="32" description="Priviledged Memory Frame  2 MasteriD Protection Register"></register>
    -  <register id="PPCS4MstId" acronym="PPCS4MstId" offset="0x5CC" width="32" description="Priviledged Memory Frame  4 MasteriD Protection Register"></register>
    -  <register id="PPCS6MstId" acronym="PPCS6MstId" offset="0x5D0" width="32" description="Priviledged Memory Frame  6 MasteriD Protection Register"></register>
    -  <register id="PPCS8MstId" acronym="PPCS8MstId" offset="0x5D4" width="32" description="Priviledged Memory Frame  8 MasteriD Protection Register"></register>
    -  <register id="PPCS10MstId" acronym="PPCS10MstId" offset="0x5D8" width="32" description="Priviledged Memory Frame  10 MasteriD Protection Register"></register>
    -  <register id="PPCS12MstId" acronym="PPCS12MstId" offset="0x5DC" width="32" description="Priviledged Memory Frame  12 MasteriD Protection Register"></register>
    -  <register id="PPCS14MstId" acronym="PPCS14MstId" offset="0x5E0" width="32" description="Priviledged Memory Frame  14 MasteriD Protection Register"></register>
    +  <register id="PPSE0MstId_L" acronym="PPSE0MstId_L" offset="0x440" width="32" description="Privileged Peripheral Extended Frame 0 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE0MstId_H" acronym="PPSE0MstId_H" offset="0x444" width="32" description="Privileged Peripheral Extended Frame 0 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE1MstId_L" acronym="PPSE1MstId_L" offset="0x448" width="32" description="Privileged Peripheral Extended Frame 1 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE1MstId_H" acronym="PPSE1MstId_H" offset="0x44C" width="32" description="Privileged Peripheral Extended Frame 1 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE2MstId_L" acronym="PPSE2MstId_L" offset="0x450" width="32" description="Privileged Peripheral Extended Frame 2 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE2MstId_H" acronym="PPSE2MstId_H" offset="0x454" width="32" description="Privileged Peripheral Extended Frame 2 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE3MstId_L" acronym="PPSE3MstId_L" offset="0x458" width="32" description="Privileged Peripheral Extended Frame 3 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE3MstId_H" acronym="PPSE3MstId_H" offset="0x45C" width="32" description="Privileged Peripheral Extended Frame 3 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE4MstId_L" acronym="PPSE4MstId_L" offset="0x460" width="32" description="Privileged Peripheral Extended Frame 4 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE4MstId_H" acronym="PPSE4MstId_H" offset="0x464" width="32" description="Privileged Peripheral Extended Frame 4 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE5MstId_L" acronym="PPSE5MstId_L" offset="0x468" width="32" description="Privileged Peripheral Extended Frame 5 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE5MstId_H" acronym="PPSE5MstId_H" offset="0x46C" width="32" description="Privileged Peripheral Extended Frame 5 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE6MstId_L" acronym="PPSE6MstId_L" offset="0x470" width="32" description="Privileged Peripheral Extended Frame 6 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE6MstId_H" acronym="PPSE6MstId_H" offset="0x474" width="32" description="Privileged Peripheral Extended Frame 6 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE7MstId_L" acronym="PPSE7MstId_L" offset="0x478" width="32" description="Privileged Peripheral Extended Frame 7 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE7MstId_H" acronym="PPSE7MstId_H" offset="0x47C" width="32" description="Privileged Peripheral Extended Frame 7 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE8MstId_L" acronym="PPSE8MstId_L" offset="0x480" width="32" description="Privileged Peripheral Extended Frame 8 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE8MstId_H" acronym="PPSE8MstId_H" offset="0x484" width="32" description="Privileged Peripheral Extended Frame 8 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE9MstId_L" acronym="PPSE9MstId_L" offset="0x488" width="32" description="Privileged Peripheral Extended Frame 9 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE9MstId_H" acronym="PPSE9MstId_H" offset="0x48C" width="32" description="Privileged Peripheral Extended Frame 9 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE10MstId_L" acronym="PPSE10MstId_L" offset="0x490" width="32" description="Privileged Peripheral Extended Frame 10 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE10MstId_H" acronym="PPSE10MstId_H" offset="0x494" width="32" description="Privileged Peripheral Extended Frame 10 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE11MstId_L" acronym="PPSE11MstId_L" offset="0x498" width="32" description="Privileged Peripheral Extended Frame 11 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE11MstId_H" acronym="PPSE11MstId_H" offset="0x49C" width="32" description="Privileged Peripheral Extended Frame 11 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE12MstId_L" acronym="PPSE12MstId_L" offset="0x4A0" width="32" description="Privileged Peripheral Extended Frame 12 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE12MstId_H" acronym="PPSE12MstId_H" offset="0x4A4" width="32" description="Privileged Peripheral Extended Frame 12 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE13MstId_L" acronym="PPSE13MstId_L" offset="0x4A8" width="32" description="Privileged Peripheral Extended Frame 13 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE13MstId_H" acronym="PPSE13MstId_H" offset="0x4AC" width="32" description="Privileged Peripheral Extended Frame 13 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE14MstId_L" acronym="PPSE14MstId_L" offset="0x4B0" width="32" description="Privileged Peripheral Extended Frame 14 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE14MstId_H" acronym="PPSE14MstId_H" offset="0x4B4" width="32" description="Privileged Peripheral Extended Frame 14 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE15MstId_L" acronym="PPSE15MstId_L" offset="0x4B8" width="32" description="Privileged Peripheral Extended Frame 15 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE15MstId_H" acronym="PPSE15MstId_H" offset="0x4BC" width="32" description="Privileged Peripheral Extended Frame 15 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE16MstId_L" acronym="PPSE16MstId_L" offset="0x4C0" width="32" description="Privileged Peripheral Extended Frame 16 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE16MstId_H" acronym="PPSE16MstId_H" offset="0x4C4" width="32" description="Privileged Peripheral Extended Frame 16 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE17MstId_L" acronym="PPSE17MstId_L" offset="0x4C8" width="32" description="Privileged Peripheral Extended Frame 17 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE17MstId_H" acronym="PPSE17MstId_H" offset="0x4CC" width="32" description="Privileged Peripheral Extended Frame 17 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE18MstId_L" acronym="PPSE18MstId_L" offset="0x4D0" width="32" description="Privileged Peripheral Extended Frame 18 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE18MstId_H" acronym="PPSE18MstId_H" offset="0x4D4" width="32" description="Privileged Peripheral Extended Frame 18 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE19MstId_L" acronym="PPSE19MstId_L" offset="0x4D8" width="32" description="Privileged Peripheral Extended Frame 19 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE19MstId_H" acronym="PPSE19MstId_H" offset="0x4DC" width="32" description="Privileged Peripheral Extended Frame 19 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE20MstId_L" acronym="PPSE20MstId_L" offset="0x4E0" width="32" description="Privileged Peripheral Extended Frame 20 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE20MstId_H" acronym="PPSE20MstId_H" offset="0x4E4" width="32" description="Privileged Peripheral Extended Frame 20 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE21MstId_L" acronym="PPSE21MstId_L" offset="0x4E8" width="32" description="Privileged Peripheral Extended Frame 21 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE21MstId_H" acronym="PPSE21MstId_H" offset="0x4FC" width="32" description="Privileged Peripheral Extended Frame 21 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE22MstId_L" acronym="PPSE22MstId_L" offset="0x4F0" width="32" description="Privileged Peripheral Extended Frame 22 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE22MstId_H" acronym="PPSE22MstId_H" offset="0x4F4" width="32" description="Privileged Peripheral Extended Frame 22 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE23MstId_L" acronym="PPSE23MstId_L" offset="0x4F8" width="32" description="Privileged Peripheral Extended Frame 23 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE23MstId_H" acronym="PPSE23MstId_H" offset="0x4FC" width="32" description="Privileged Peripheral Extended Frame 23 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE24MstId_L" acronym="PPSE24MstId_L" offset="0x500" width="32" description="Privileged Peripheral Extended Frame 24 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE24MstId_H" acronym="PPSE24MstId_H" offset="0x504" width="32" description="Privileged Peripheral Extended Frame 24 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE25MstId_L" acronym="PPSE25MstId_L" offset="0x508" width="32" description="Privileged Peripheral Extended Frame 25 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE25MstId_H" acronym="PPSE25MstId_H" offset="0x50C" width="32" description="Privileged Peripheral Extended Frame 25 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE26MstId_L" acronym="PPSE26MstId_L" offset="0x510" width="32" description="Privileged Peripheral Extended Frame 26 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE26MstId_H" acronym="PPSE26MstId_H" offset="0x514" width="32" description="Privileged Peripheral Extended Frame 26 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE27MstId_L" acronym="PPSE27MstId_L" offset="0x518" width="32" description="Privileged Peripheral Extended Frame 27 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE27MstId_H" acronym="PPSE27MstId_H" offset="0x51C" width="32" description="Privileged Peripheral Extended Frame 27 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE28MstId_L" acronym="PPSE28MstId_L" offset="0x520" width="32" description="Privileged Peripheral Extended Frame 28 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE28MstId_H" acronym="PPSE28MstId_H" offset="0x524" width="32" description="Privileged Peripheral Extended Frame 28 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE29MstId_L" acronym="PPSE29MstId_L" offset="0x528" width="32" description="Privileged Peripheral Extended Frame 29 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE29MstId_H" acronym="PPSE29MstId_H" offset="0x52C" width="32" description="Privileged Peripheral Extended Frame 29 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE30MstId_L" acronym="PPSE30MstId_L" offset="0x530" width="32" description="Privileged Peripheral Extended Frame 30 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE30MstId_H" acronym="PPSE30MstId_H" offset="0x534" width="32" description="Privileged Peripheral Extended Frame 30 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PPSE31MstId_L" acronym="PPSE31MstId_L" offset="0x538" width="32" description="Privileged Peripheral Extended Frame 31 (Quadrant 0 and 1) MasteriD Protection Register"></register>
    +  <register id="PPSE31MstId_H" acronym="PPSE31MstId_H" offset="0x53C" width="32" description="Privileged Peripheral Extended Frame 31 (Quadrant 2 and 3) MasteriD Protection Register"></register>
    +  <register id="PCS0MstId" acronym="PCS0MstId" offset="0x540" width="32" description="Memory Frame  0 MasteriD Protection Register"></register>
    +  <register id="PCS2MstId" acronym="PCS2MstId" offset="0x544" width="32" description="Memory Frame  1 MasteriD Protection Register"></register>
    +  <register id="PCS4MstId" acronym="PCS4MstId" offset="0x548" width="32" description="Memory Frame  2 MasteriD Protection Register"></register>
    +  <register id="PCS6MstId" acronym="PCS6MstId" offset="0x54C" width="32" description="Memory Frame  3 MasteriD Protection Register"></register>
    +  <register id="PCS8MstId" acronym="PCS8MstId" offset="0x550" width="32" description="Memory Frame  4 MasteriD Protection Register"></register>
    +  <register id="PCS10MstId" acronym="PCS10MstId" offset="0x554" width="32" description="Memory Frame  5 MasteriD Protection Register"></register>
    +  <register id="PCS12MstId" acronym="PCS12MstId" offset="0x558" width="32" description="Memory Frame  6 MasteriD Protection Register"></register>
    +  <register id="PCS14MstId" acronym="PCS14MstId" offset="0x55C" width="32" description="Memory Frame  7 MasteriD Protection Register"></register>
    +  <register id="PCS16MstId" acronym="PCS16MstId" offset="0x560" width="32" description="Memory Frame  8 MasteriD Protection Register"></register>
    +  <register id="PCS18MstId" acronym="PCS18MstId" offset="0x564" width="32" description="Memory Frame  9 MasteriD Protection Register"></register>
    +  <register id="PCS20MstId" acronym="PCS20MstId" offset="0x568" width="32" description="Memory Frame  10 MasteriD Protection Register"></register>
    +  <register id="PCS22MstId" acronym="PCS22MstId" offset="0x56C" width="32" description="Memory Frame  11 MasteriD Protection Register"></register>
    +  <register id="PCS24MstId" acronym="PCS24MstId" offset="0x570" width="32" description="Memory Frame  12 MasteriD Protection Register"></register>
    +  <register id="PCS26MstId" acronym="PCS26MstId" offset="0x574" width="32" description="Memory Frame  13 MasteriD Protection Register"></register>
    +  <register id="PCS28MstId" acronym="PCS28MstId" offset="0x578" width="32" description="Memory Frame  14 MasteriD Protection Register"></register>
    +  <register id="PCS30MstId" acronym="PCS30MstId" offset="0x57C" width="32" description="Memory Frame  15 MasteriD Protection Register"></register>
    +  <register id="PCS32MstId" acronym="PCS32MstId" offset="0x580" width="32" description="Memory Frame  16 MasteriD Protection Register"></register>
    +  <register id="PCS34MstId" acronym="PCS34MstId" offset="0x584" width="32" description="Memory Frame  17 MasteriD Protection Register"></register>
    +  <register id="PCS36MstId" acronym="PCS36MstId" offset="0x588" width="32" description="Memory Frame  18 MasteriD Protection Register"></register>
    +  <register id="PCS38MstId" acronym="PCS38MstId" offset="0x58C" width="32" description="Memory Frame  19 MasteriD Protection Register"></register>
    +  <register id="PCS40MstId" acronym="PCS40MstId" offset="0x590" width="32" description="Memory Frame  20 MasteriD Protection Register"></register>
    +  <register id="PCS42MstId" acronym="PCS42MstId" offset="0x594" width="32" description="Memory Frame  21 MasteriD Protection Register"></register>
    +  <register id="PCS44MstId" acronym="PCS44MstId" offset="0x598" width="32" description="Memory Frame  22 MasteriD Protection Register"></register>
    +  <register id="PCS46MstId" acronym="PCS46MstId" offset="0x59C" width="32" description="Memory Frame  23 MasteriD Protection Register"></register>
    +  <register id="PCS48MstId" acronym="PCS48MstId" offset="0x5A0" width="32" description="Memory Frame  24 MasteriD Protection Register"></register>
    +  <register id="PCS50MstId" acronym="PCS50MstId" offset="0x5A4" width="32" description="Memory Frame  25 MasteriD Protection Register"></register>
    +  <register id="PCS52MstId" acronym="PCS52MstId" offset="0x5A8" width="32" description="Memory Frame  26 MasteriD Protection Register"></register>
    +  <register id="PCS54MstId" acronym="PCS54MstId" offset="0x5AC" width="32" description="Memory Frame  27 MasteriD Protection Register"></register>
    +  <register id="PCS56MstId" acronym="PCS56MstId" offset="0x5B0" width="32" description="Memory Frame  28 MasteriD Protection Register"></register>
    +  <register id="PCS58MstId" acronym="PCS58MstId" offset="0x5B4" width="32" description="Memory Frame  29 MasteriD Protection Register"></register>
    +  <register id="PCS60MstId" acronym="PCS60MstId" offset="0x5B8" width="32" description="Memory Frame  30 MasteriD Protection Register"></register>
    +  <register id="PCS62MstId" acronym="PCS62MstId" offset="0x5BC" width="32" description="Memory Frame  31 MasteriD Protection Register"></register>
    +  <register id="PPCS0MstId" acronym="PPCS0MstId" offset="0x5C0" width="32" description="Priviledged Memory Frame  0 MasteriD Protection Register"></register>
    +  <register id="PPCS2MstId" acronym="PPCS2MstId" offset="0x5C4" width="32" description="Priviledged Memory Frame  1 MasteriD Protection Register"></register>
    +  <register id="PPCS4MstId" acronym="PPCS4MstId" offset="0x5C8" width="32" description="Priviledged Memory Frame  2 MasteriD Protection Register"></register>
    +  <register id="PPCS6MstId" acronym="PPCS6MstId" offset="0x5CC" width="32" description="Priviledged Memory Frame  3 MasteriD Protection Register"></register>
    +  <register id="PPCS8MstId" acronym="PPCS8MstId" offset="0x5D0" width="32" description="Priviledged Memory Frame  4 MasteriD Protection Register"></register>
    +  <register id="PPCS10MstId" acronym="PPCS10MstId" offset="0x5D4" width="32" description="Priviledged Memory Frame  5 MasteriD Protection Register"></register>
    +  <register id="PPCS12MstId" acronym="PPCS12MstId" offset="0x5D8" width="32" description="Priviledged Memory Frame  6 MasteriD Protection Register"></register>
    +  <register id="PPCS14MstId" acronym="PPCS14MstId" offset="0x5DC" width="32" description="Priviledged Memory Frame  7 MasteriD Protection Register"></register >
    +  <register id="PCREXTMsTId" acronym="PCREXTMsTId" offset="0x5E0" width="32" description="Master-ID Protection Register for External PCR"></register>
     </module>
    \ No newline at end of file

     

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Hello Anthony, Hello Zhaohong,

    thanks for following up this topic.

    Yes, you are right that we have so far used a special package for LC6357 device which is delivered by TI field support team. I also found the file name xxx5.3.0.xml.

    I have installed CCS6.0.0.00190. But as I tried to create a target configuration for LC4357, I can't find this device in the "board or Device" list. The list runs up to TMS570LS3137. It seems that CCS6.0 doesn't have the LC4357 support by default (as in CCS5.5). If this is the case, where can I download the special package for LC4357?

    Thanks and regards,

    Libo


     

  • 0 in reply to Libo Luo
    TI__Guru 68920 points

    Hi Libo,

    Sorry - the LC4357 is not in the stock 6.0.0 installer.  After you install 6.0.0,  you need to run the update / install new software processes to get the updates for 6.0.0.   We will be in the stock 6.0.1 installer though and I believe this should be coming out quite soon.

     

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Hi Anthony,

    I have tried to update with "Install New Software". Unfortunately I couldn't connect to the websites listed there.


    If I select one website and I will see error message like this

    "Unable to connect to repository http://software-dl.ti.com/ccs/esd/CCSv6/Updates/content.xml
    Unable to connect to repository http://software-dl.ti.com/ccs/esd/CCSv6/Updates/content.xml
    Connection to http://software-dl.ti.com refused"

    I also tried to open the address "http://software-dl.ti.com/ccs/esd/CCSv6/Updates" directly in Internet Explorer. And I got this message:

    "File not found"

    My firewall SW is activated. Maybe this could be the reason? In this case I think at least I can reach the website through IE.

    Regards,

    Libo

  • 0 in reply to Libo Luo
    TI__Guru 68920 points

    Libo,

    Those do sound like they might be either firewall or proxy issues.  You can set the proxy that CCS uses through the menu Window->General->Network Connections.  

    I also found out that the emulation pack required as a prerequesite for the Hercules pack 6.0.3 which adds support for the TMS570LC4357 and the RM57L843 was pulled temporarily due to a problem that it created for C2000 users.   It is back up as of now however, and here is what the update looks like from a fresh CCSv6 install (with just ARM 32-bit MCUs installed)

    Hopefully you can get support for the firewall or proxy problem and then access the updates above.

    NOTE:  I belive you are using the TMS570LC4357.  I posted a "Sticky" note about CPU Reset and System Reset fixes and you will need to apply these workarounds for this lastest pack 5.507.1 as well.   We are working on a fix but expect to included it in a release in mid july so between now and then you'll need these workarounds. 

     

     

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Hi Anthony,

    Yes, I use TMS570LC4357. With the proxy server set, I can now install the updates including the Emulator pack 5.1.507.1. How can I now get the workarounds you mentioned?

    Regards,

    Libo

  • 0 in reply to Libo Luo
    TI__Guru 68920 points

    Great.  Workarounds I mentioned are described in the sticky post http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/350161.aspx

    You have 2 things to do manually - one is uncheck a box in the CCXML and the other is to add a bit of code to the GEL file you are using.  Details are described in the post.

    Best Regards,

    Anthony

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Hi Anthony,


    I have unchecked the box in the CCXML. The GEL file is not changed yet. I have tried to start a debug session and see the following message window:

    I have activated the same license file as for CCS5.5. And in CCS5.5 I can debug with XDS510 emulators. How can I update the license file for CCS6.0?

    Thanks and regards,

    Libo

  • 0 in reply to Libo Luo
    TI__Guru 68920 points

    Libo,

    I can't see the screenshot - assume it's telling you that you have the free license that works only with the XDS100 by the context of the rest of the message.    There is some help on that here:  http://processors.wiki.ti.com/index.php/Licensing_-_CCS.

    Best Regards,

    Anthony

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Hi Anthony,

    I have read the Wiki. There it mentions activation code etc. So far I have used floating license in CCS5.5. I assume we still only have the floating license for CCS6.0 in the company. Do we need to change something in the license file so that it works also .for CCS6.0?

    Thanks and regards,

    Libo

  • 0 in reply to Libo Luo
    TI__Guru 68920 points

    Libo,

    If you are using a network floating license, then you may need to track down the owner / license manager and have them make a license that works for CCSv6 available on the server.    In the meantime - you might go with the evaluation license so you have time to work out the update to your floating license.

  • 0 in reply to Anthony F. Seely
    Intellectual 940 points

    Anthony,

    I have switched to evaluation license, and changed the tms570lc43xx.gel as described in the sticky note. I can launch a target configuration with TMS570LC4357. But if I try to connect to the target, after about 1-2 minutes, I get the follow message in the console:

    CortexR5: JTAG Communication Error: Error 0xA00020A0/-1250 Error during: Execution, Target Communication, Control,  Device driver: Lost USB connection to emulator. You should ABORT and restart to re-establish the USB link.  
    IcePick: Power Failure on Target CPU
    Dap: Power Failure on Target CPU

    And in the debug tab, I see the text "Spectrum Digital XDS510USB Emulator_0/CortexR5 (Disconnected: No Power)".

    If I now click on "Test Connection", I get this message:

    "

    [Start: Spectrum Digital XDS510USB Emulator_0]

    Execute the command:

    %ccs_base%/emulation/drivers/sdjtag.exe -f %boarddatafile% -v -X reset -X scantest

    [Result]

    ** BoardFilePath: C:\Users\luol1\AppData\Local\TEXASI~1\CCS\ti\0\0\BrdDat\testBoard.dat
    ** Resetting Emulator
         ERROR -- XDS510USB Reset Failed
         ERROR -- Check power to your emulator/eZdsp
         ERROR -- Then check your port address

    [End: Spectrum Digital XDS510USB Emulator_0]
    "

    Then I stopped the debug session, and switched off the power on the HDK board, switched on, and then click the "Test Connection" button again, now test passes:

    [Start: Spectrum Digital XDS510USB Emulator_0]

    Execute the command:

    %ccs_base%/emulation/drivers/sdjtag.exe -f %boarddatafile% -v -X reset -X scantest

    [Result]

    ** BoardFilePath: C:\Users\luol1\AppData\Local\TEXASI~1\CCS\ti\0\0\BrdDat\testBoard.dat
    ** Resetting Emulator
     -- Emulator is Reset
    ** Emulator Scan Test
     -- Found JTAG IR Length of 6
     -- Found 1 device(s) in the scan chain

    [End: Spectrum Digital XDS510USB Emulator_0]

    If I start CCS5.5 which is still parallel installed on the computer, and try to launch a target configuration, the CCS window just disappeared after a few seconds.

    Any suggestions?

    Thanks and regards,

    Libo

  • 0 in reply to Libo Luo
    Intellectual 940 points

    Anthony,

    I can't debug with CCS6.0/CCS5.5.

    I have done the following test:

    1. Start CCS6.0; Don't launch any target. Click on the "Test Connection" button for the TMS570LC4357 target. The test passes and the test message in the previous post is displayed.

    [Start: Spectrum Digital XDS510USB Emulator_0]

    Execute the command:

    %ccs_base%/emulation/drivers/sdjtag.exe -f %boarddatafile% -v -X reset -X scantest

    [Result]

    ** BoardFilePath: C:\Users\luol1\AppData\Local\TEXASI~1\CCS\ti\0\0\BrdDat\testBoard.dat
    ** Resetting Emulator
     -- Emulator is Reset
    ** Emulator Scan Test
     -- Found JTAG IR Length of 6
     -- Found 1 device(s) in the scan chain

    [End: Spectrum Digital XDS510USB Emulator_0]

    2. Launch the TMS570LC4357 target.

    3. Click on the "Connect Target" button. After about 1-2 minutes, the error message as in the previous post is displayed.

    CortexR5: JTAG Communication Error: Error 0xA00020A0/-1250 Error during: Execution, Target Communication, Control,  Device driver: Lost USB connection to emulator. You should ABORT and restart to re-establish the USB link.  
    IcePick: Power Failure on Target CPU
    Dap: Power Failure on Target CPU

    4. Click the "Test Connection" button, I get the error message:

    [Start: Spectrum Digital XDS510USB Emulator_0]

    Execute the command:

    %ccs_base%/emulation/drivers/sdjtag.exe -f %boarddatafile% -v -X reset -X scantest

    [Result]

    ** BoardFilePath: C:\Users\luol1\AppData\Local\TEXASI~1\CCS\ti\0\0\BrdDat\testBoard.dat
    ** Resetting Emulator
         ERROR -- XDS510USB Reset Failed
         ERROR -- Check power to your emulator/eZdsp
         ERROR -- Then check your port address

    [End: Spectrum Digital XDS510USB Emulator_0]

    5. Exit CCS6.0.

    6. Restart CCS6.0. Don't launch any target. Click on "Test Connection". The same error message as in Step 4 is displayed.

    7. Switch off and on the power of the HDK board. Click on "Test Connection". The test passes.

    It seems that the CCS6.0 with the patch you have mentioned still has problem with Reset or System reset.

    Please advise me how to proceed.

    Thanks and regards,

    Libo

  • 0 in reply to Libo Luo
    Intellectual 940 points

    Anthony,

    I was informed by TI FAE that we don't have the CCS6.0 license. So I have uninstalled CCS6.0.

    Because CCS5.5 didn't work any more. I have asked for help in a new thread and was told to reinstall CCS5.5 in a new/different folder.

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/p/351957/1233775.aspx#1233775

    After that, I can debug with CCS5.5. But I don't know why the previous CCS5.5 under the default folder didn't work.  Error log files are attached to that thread. Hopefully I could get some explanation.

    As my original question at the beginning of this thread was answered, I will mark this question as answered for now.

    Thanks and regards,

    Libo