Hello Hercules team,
I have implemented the NHET LBIST for TMS570LC4357 using STC2. As the test run time is quite long, I am trying to reduce the run time by reducing the clock prescaler register.
I noticed that the NHET LBIST failed if the clock prescaler was set to 0 for NHET1 and NHET2.
The configuration looks like this:
- STCGCR0: Test interval counter: 1, Idle cycle: 1, Restart from interval 0.
- STCGCR1: parallel mode
- STCTPR: timeout preload: 0x7FFFFFFF
- STCSCSCR: self check disabled (no error injection)
- STCCLKDIV: clock prescaler 0 for both cores (NHET1 and NHET2)
After the test is finished, the STCGSTAT register is 0x503 and the STCFSTAT register is 0x003. So both NHET1 and NHET2 test failed.
If I change the clock prescaler for both NHETs to 1, then the same test passed.
In my test the VCLK2 is 32MHZ, so STC clock is 32MHz if the prescaler is 0, and it is 16MHz if the prescaler is 1.
In the TMS570LC4357 TRM, Tab. 10-7, the STC2 clock can be set up to 110MHz. So the STC2 clock in my test is still in a quite lower range and timing should not be the problem.
Could you please provide some insight here?
Thank you and regards,
Libo
