Issue facing:
When we try to write GPIO_PORTL_DIR_R, it is not writing and going to the Fault ISR.
Background details:
We have configured as follows.
// Clock power source config for 25Mhz
SYSCTL_RCC_R = 0x00183E80;
// Clock source eneable for GPIO
SYSCTL_RCGC2_R = 0X00000FFF;
SYSCTL_RCGCGPIO_R = 0x0000FFFF;
During debugging, SYSCTL_RCGCGPIO_R shows 0x3F (R0 to R5 are set i.e Enable and provide a clock to GPIO PORT A to PORT F are only set).
Remaining Ports PORT G - PORT P are not provided with clock enable.
We understand if Enable and provide a clock to GPIO PORT L is set, then DIR register of PORT L can be written.
Kindly guide us early as possible to get the proper working condition.
thanks in advance.
Prabhu.N