• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 30 subscribers
  • Views 681 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137 STC Details

Charles Johnston
Expert 2690 points

Hello,

The TRM, SPMU499b, provides a good overview of the STC and how to use it.  Where can I find details on what is actually tested?  For example:

1) Does the STC only exercise existing failure detection mechanisms inside the ARM core, or does it detect failures that would not otherwise be caught during normal operation?  (i.e., does it only detect failures in the failure detection mechanisms?)

2) Is there a description of tests performed with each interval?

3) How can we decode the MISR values?

Thanks, Charlie Johnston

  • 0
    TI__Guru 68920 points

    Charlie,

    It's testing the CPUs - see figure 8-1.

    Charles Johnston said:
    1) Does the STC only exercise existing failure detection mechanisms inside the ARM core, or does it detect failures that would not otherwise be caught during normal operation?  (i.e., does it only detect failures in the failure detection mechanisms?)

    No - the self test tests the CPUs in entirity (at least to the % coverage levels in next answer) and it will pick up errors that might otherwise be latent - not showing up just by the normal core-compare logic in normal operation;  for example maybe it's a register that is used rarely only when an obscure condition occurs - this would probably be picked up by the STC during a regular interval where it may not be picked up by the core compare logic until the condition occurs that makes it visible at the CPU boundary.

    Charles Johnston said:
    2) Is there a description of tests performed with each interval?

    No there is only a cumulative % test coverage after each interval

    Charles Johnston said:
    3) How can we decode the MISR values?

     

    you really can't - it's a similar question to asking which memory location is bad given a bad CRC value.  It's highly 'compressed' and all you can get is a pass/fail.

  • 0 in reply to Anthony F. Seely
    Expert 2690 points

    Hi Anthony,

    So in regards to 1), the STC does not add any failure detection capability, it just catches any errors earlier.

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Guru 68920 points

    Hi Charlie,

    I don't think that's exactly correct.   Take an example of a fault in a register or logic that is never used in your application.  Given the high fault coverage of the STC it will likely catch this.    So in that sense it should be more complete.

    But I think the purpose is different and the best way to understand would be to show how each hardware feature helps when it comes time to perform the various calculations involved in the fault coverage analysis.    The latent metrics are where the BIST tests help a lot whereas online testing like core compare logic and ECC only check what is being used at any given moment.

     

  • 0 in reply to Anthony F. Seely
    Expert 2690 points

    Thanks, Anthony.

    Charlie Johnston

  • 0 in reply to Charles Johnston
    Expert 2690 points

    Hi Anthony,

    Sorry to keep bugging you about this, but we're trying to see if we lose any actual fault detection by not running the STC. 

    1) Are all latent failures caught by the STC also detected when they occur in normal operation?

    2) Could there be a case of the STC catching an obscure latent failure that would have an effect on processing but is not visible at the CPU boundary?

    Thanks, Charlie Johnston

  • 0 in reply to Charles Johnston
    TI__Guru 68920 points

    Charlie,

    for (1)  - I believe the proper idea is that the STC takes the faults that would otherwise be latent and reduces them by making them detected (by the STC).   

    for (2) - I suppose this could happen - you might have two faults that combine to produce the same result at the CPU boundary as no faults but the STC catches them.   but this is probably really obscure.

    I think you are getting in pretty deep now and should probably get in touch w. our safety forum.  Have you been signed up for the safety forum? (it is private).

  • 0 in reply to Anthony F. Seely
    Expert 2690 points

    Hi Anthony,

    This has been very helpful.  I do belong to the SafeTI Forum.  If I have any deeper questions on this topic, I'll bring it up there.

    Thanks again, Charlie Johnston