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Fss is pulled high at the end of each byte in SSI legacy mode

Other Parts Discussed in Thread: TM4C1294NCPDT

Hi,  

I have a question about SSI legacy mode in 1294 launchpad. I am using the example "SPI loopback", which could be found at "TI-RTOS for TivaC"/"TivaC Series"/"Tiva TM4C1294NCPDT"/"Driver Examples"/"TI Examples"/"SPI loopback". Without any code change, I found that Fss is pulled high at the end of each byte sent by master. I'd like Fss to be low during continuous transmission and be pulled high only at the end of all bytes.    

The code to send are copied here:  

 

Void masterTaskFxn (UArg arg0, UArg arg1)
{
    SPI_Handle masterSpi;
    SPI_Transaction masterTransaction;
    bool transferOK;

    /* Initialize SPI handle as default master */
    masterSpi = SPI_open(Board_SPI0, NULL);
    if (masterSpi == NULL) {
        System_abort("Error initializing SPI\n");
    }
    else {
        System_printf("SPI initialized\n");
    }

    /* Initialize master SPI transaction structure */
    masterTransaction.count = SPI_MSG_LENGTH;
    masterTransaction.txBuf = (Ptr)masterTxBuffer;
    masterTransaction.rxBuf = (Ptr)masterRxBuffer;

    /* Initiate SPI transfer */
    transferOK = SPI_transfer(masterSpi, &masterTransaction);

       ......

 

The register value for SSI_CR1 in SSI2 is:

I have some questions:
 1. FSSHLDFRM is 0. According to 1294's user guide Table 17.3, Fss should be kept low during continuous transmission if FSSHLDFRM is 0 in legacy mode. But it isn't.
 2. I have tried modifying FSSHLDFRM to 1, but I found FSS is always low, even before and after the SSI transmission.
 What does the value in SSI_PP mean? I found the values are not consistent with those in SSI_CR1.
 3. How to make FSS low during the continuous transmission?
 
 Thanks

  • Hello Jianyi,

    The FSS will pulse after every byte if the Data Buffer runs out before the next word is written in the legacy frame. When FSSHLDFRM=1 the user has to ensure that after SSI transmission is one word short of completion, the FSSHDLFRM be made 0 and then the last wrod written so that after transmission the FSS is made 1.

    SSI_PP is the properties register which tells the user what features are usable for the peripheral.

    Regards

    Amit