IIC SDA and SCL line not pulling High after pin muxing

Sanchit Mehra said:

SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN);

I don't think an underline at SYSCTL_OSC_MAIN is correct.

-kel

I removed SYSCTL_OSC_MAIN paramter and set

SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_25MHZ);

But still Pins are not getting pulled up ...
Is there can be any clock frequency issue in this ? while selecting the SYSCTL_SYSDIV_2_5 and PLL?

Regards,

Sanchit

Apart from removing the SYSCTL_OSC_MAIN ,

I debugged the I2C registers and found

I2C_MCS_RUN and I2C_MCS_BUSY set as 1.

please find attached snapshot of registers status.

This register status is at the start of debug.

Is this something weird or Ok ?

Kindly suggest.

Regards,

Sanchit

Hello Sanchit,

That is correct that you do not need External pull Up. But then configuring the GPIO for I2C does not enable the pull up automatically. This has to be done by writing the corresponding pin in GPIO Port PUR register. Also do note that the internal Pull Up is a weak pull up and may affect both noise resilience and baud rate due to slow rise. So it would be advisable to have external pull up on the board

Regards

Amit

Sanchit Mehra said:

I removed SYSCTL_OSC_MAIN paramter and set

I did not imply that you remove the SYSCTL_OSC_MAIN. I am implying to just remove the "underline". See, SysCtlClockSet at Tivaware Peripheral Library User's Guide.

What Tiva kit are your using?

- kel

Hi Kel, 

I am using TIVA  C Series TM4C129x.

as being advised that corresponding GPIO PIN has to be written in GPIO PUR register .

Is it mandatory to do it at register level ?
Or is it the exposed API such as GPIOPinConfigure which could do this job ?

Thanks,

Sanchit

Hello Sanchit

There is no explicit function to enable the PUR. You will have to call the lower level HWREG macro or put external pull up.

Regards

Amit

Hi,

Hello Petrei.

An excellent observation, that may cause really erroneous results later. Thanks again...

Regards

Amit

Thanks !

SCL and SDA line are pulled high  but now I see in oscilloscope that SCL line , clock is not properly generated. while in SDA line, I can see the data from the wave on SDA line.

Here is the code :

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C8);

ROM_GPIOPinTypeI2CSCL(GPIO_PORTD_BASE, GPIO_PIN_2);

ROM_GPIOPinTypeI2C(GPIO_PORTD_BASE, GPIO_PIN_3);

ROM_GPIOPinConfigure(GPIO_PD2_I2C8SCL);

ROM_GPIOPinConfigure(GPIO_PD3_I2C8SDA);

ROM_I2CMasterEnable(I2C8_BASE);

ROM_I2CMasterInitExpClk(I2C8_BASE,SysCtlClockGet(),false);

ROM_I2CMasterSlaveAddrSet(I2C8_BASE,0x30,true);

// Master initiating a read from slave.

while( ROM_I2CMasterBusBusy(I2C8_BASE) )

{

}

ROM_I2CMasterControl(I2C8_BASE,I2C_MASTER_CMD_SINGLE_RECEIVE);

The wave form in SDA line is proper but SCL line is weird.

Please suggest. 

Hello Sanchit,

Please note that SCL will have the "Shark Fin" waveform due to Pull Up when sending 1 and drive when sending 0.

Put a snapshot from the scope, so that we can see if the weird is indeed "Shark Fin" Pattern.

Regards

Amit

Hi Amit,

pls find atatched the snapshot of the waveform.

Red Clr is SCL line

Yellow clr is SDA line waveform.

and also attached the register status during this state.

Thanks,

Sanchit

Hello Sanchit,

The SCL is clearly "weird". Is this with the Internal Pull Up? Can you add an external pull up on the SCL of ~4.7K

Looking at the SCL line it seems there is a very large capacitive load.

Regards

Amit

Hello Amit,

There is one capacitance of 100n on the SCL line .

I will remove it and try ,

moreover , is the clock line frequency effected by system clock set by

ui32SysClock =SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |

                                       SYSCTL_OSC_MAIN |

                                       SYSCTL_USE_PLL |

                                       SYSCTL_CFG_VCO_480), 120000000);

because, when I lower this system frequency to 1000000,  the SCL line waveform becomes near to shark fin..

Does this also effecting the drive frequency of IIC ?

Regards,

Sanchit

Hello Sanchit,

Why did you put a 100nF cap on the SCL Line?

The system clock is used to derive the I2C Clock using the I2CMTPR register. We have the 120Mhz waveform. Can you send the 100MHz waveform?

Regards

Amit

Hello Amit,

As this pin was not solely being used for IIC only, there were other purposes to be met out.So this much capicitance was put.

Can we increase the slew rate of GPIO pin to overcome this much capicitance ?

May you suggest a way to read mutliple bytes from the slave ?

Thanks for your quick replies and support !

Sanchit

Hello Sanchit,

The Slew rate and drive  will only affect the low level. The High level is due to the Pull Up charging a cap. You have remove the cap.

First get a basic transfer working before we go to multiple bytes. Without the SCL it would be useless exercise.

Regards

Amit

Amit Ashara said:

First get a basic transfer working before we go to multiple bytes. Without the SCL it would be useless exercise.

Bravo - poster's, "kitchen-sink burdening" of poor SCL line - and desire to proceed further w/out "fix" - surely violates KISS!

Note that you had to, "tease out" the (unexplained) "cause" of the, "weird" SCL waveform.

Lastly - any attempt by poster/others to, "share" an I2C SCL signal line requires great care/attention to detail.  Unless the I2C slave is disabled - it will surely, "see/be impacted" by any signal activity upon SCL - even when such activity is, "Non-I2C based and/or directed!" 

Bad idea - unannounced till now - and a further, "dagger" into the safety/security/comfort provided by KISS...