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Default DMA Request Map

Szilard Lovas
Expert 1425 points

Other Parts Discussed in Thread: TMS570LS3137, TMS570LC4357, TMS570LS20216

Hi,

I'm looking for the default DMA Request Map for TMS570LS3137 or 20216.

I could found it for TMS570LC4357 only, but as I've seen it must be different because of two (A,B) DMA ports.

I've also tried to found  information about altering the default configuration without only success.

Could you give me a clue, thank you: Szilárd

  • 0
    TI__Guru 59540 points

    Hello Szilard,

    The default DMA request map can be found in the datasheets.

    For the TMS570LS3137 it is in SPNS162b.pdf (http://www.ti.com/litv/pdf/spns162b) in section 4.16.2, table 4-33

    For TMS570LS20216 it is in SPNS141f.pdf (http://www.ti.com/litv/pdf/spns141f)  in section 4.2, table 4-3

  • 0
    TI__Guru 59540 points

    In regard to how to adjust the DMA request assignments, this can be found in the TRM. Specifically, look at the definitions for "DMA Request Assignment Register 0",  "DMA Request Assignment Register 1",  "DMA Request Assignment Register 2", "DMA Request Assignment Register 3."

    A link for the TRM can be found on the product page for the specific part number. For example on the product page for TMS570LS3137 or by using this link: http://www.ti.com/lit/pdf/spnu499

  • 0 in reply to Chuck Davenport
    Expert 1425 points

    Dear Chuck,

    Thank You for the prompt response.

    I was actually looking for the mechanism that bind the peripherial to the dma request line.

    MibSPI has TXDMA_MAPx - RXDMA_MAPx for this purpuse, but maybe int the case of the other perhiperials is it hardwired isn't it?

    There is a little typo in the spnu489c.pdf (pdf page 1497) register  0x58 DREQASI1 is CH4ASI(5–0)..CH7ASI(5–0)

    (not CH8ASI(5–0)..CH11ASI(5–0)).

    regards: Szilárd

  • 0 in reply to Szilard Lovas
    TI__Guru 59540 points

    Hello Szilard,

    You are correct in that each peripheral has specific request lines assigned (hardwired) as noted in table 4-33 in the datasheet. If you search the reference guide for DMAREQ you will see many instantiations in various peripheral chapters that discuss the requests relative to the specific module. The  DREQASIx registers are then used to assign the request lines to specific DMA channels which are used to establish priorities between requests.

    Thanks for the heads up on the cut and paste error. We'll try and get that fixed in the next release.