Raw and masked GPTM interrupt Registers

Badr Mohamed

Hello,

What is the difference between GPTM Raw interrupt register and masked interrupt register ?
Both of them set their interrupt flag at time-out or match of the timer so, why two?

Is it that masked register can be priority controlled?

Thanks in advance.

Badr

over 11 years ago

0 Amit Ashara over 11 years ago

TI__Guru**** 244400 points

Hello Badr,

The Masked Interrupt Register is an AND of Raw Interrupt Status and Interrupt Mssk. The result of the Mask Interrupt Status is then OR-ed to generate an interrupt to the Cortex M4.

So if an action sets the Raw Interrupt Status but the Interrupt Mask is 0's, then no interrupt will be generated to the Cortex M4.

Regards

Amit

0 Badr Mohamed over 11 years ago in reply to Amit Ashara

Intellectual 280 points

Thanks Amit,

So, basically Raw interrupt register just a flag for all interrupts (Masked and non-masked) ?

Regards,

Badr.

0 Amit Ashara over 11 years ago in reply to Badr Mohamed

TI__Guru**** 244400 points

Hello Badr,

Yes. The RIS register will maintain the status of interrupts whether Masked or Non-Masked.

MIS will maintain when corresponding IM bit is set.

Regards

Amit

0 Badr Mohamed over 11 years ago in reply to Amit Ashara

Intellectual 280 points

Thanks Amit

Regards,

Badr

0 Long Pham1 over 11 years ago in reply to Badr Mohamed

Prodigy 40 points

Hello,

In the sample code to read ADC with Tiva C launchpad kit:

while(!ROM_ADCIntStatus(ADC0_BASE, 1, false))
{

}

What does it mean?

In the description of the "ADCIntStatus" function, the parameter bMasked is one of True or False. It's false if the raw interrupt status is required and true if the masked interrupt status is required. What is difference between True and False choice?

Thanks and Best regard!

0 Amit Ashara over 11 years ago in reply to Long Pham1

TI__Guru**** 244400 points

Hello Long,

As you correctly identified true is to return Masked Interrupt Status and false is to return Raw Interrupt Status. So in the above loop it would mean that while the Raw Interrupt Status for ADC0 Sequencer-1 is not set then wait.

Regards

Amit

0 Long Pham1 over 11 years ago in reply to Amit Ashara

Prodigy 40 points

Thanks for ur answer, Amit!

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Raw and masked GPTM interrupt Registers