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RM42 mibspi SIMO line inactive low behavior

Jonathan Thomson
Intellectual 270 points

Hi there,

First I want to note that the mibSPI module is communicating fine, but I have noticed some odd behavior on the SIMO line when it is inactive (it is inactive low, wheras all other signals are inactive high)

The RM42 in this case is the master. I have configured pull ups on all the spi lines and the clock polarity is high-inactive. This is all functioning properly, and during transmission (framed by the CS line) everything operates as normal. However, when the spi module is not active, the SIMO pin is pulled low, and it appears I cannot change this (I have tried enabling/disabling internal pullups/downs and applying external pullups). On startup (before calling mibspiInit()) the SIMO line is in an inactive high state. It is not until the mibspi module is initialized I see it go low.

Again, not a critical issue, just curious as it seems to me all lines should adopt the same inactive state, and I was wondering if I've missed something obvious. I have attached some scope traces to help illustrate the issue.

Thanks,

Jonathan

  • 0
    TI__Guru 59540 points

    Hi Jonathan,

    I believe the last bit shifted out of SOMI defines the state of the line until the next bit is shifted out. If there is an idle period between, this would be the first bit of the next transaction.

    Can you try changing the data such that the last bit transferred out will be a one and see what results you get during the idle time?

  • 0 in reply to Chuck Davenport
    Intellectual 270 points

    Hi Chuck,

    Here is an example of a communication with the MOSI line (green) "ending" on a high byte. It returns to low after the CS is released.

  • 0 in reply to Jonathan Thomson
    TI__Guru 59540 points

    Hi Jonathan,

    Can you post your format information. ie., clock phase, polarity, number of data bits, etc. I'll forward your inquiry to our designer of the module and they should be able to tell you what it should be by design. However, I believe it is dependent on the detailed setup of the module from your application. CS are always going to be inactive high as these signals are always active low and SOMI is going to depend on the slave configuration.

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Hello Jonathan,

    I confirmed with my design lead that the "resting" state of SOMI is dependent on the combinations of POLARITY and PHASE.

    For SIMO, these pins are tri-stated at the completion of a transmission so it's resting state is influenced by the pulls selected.

    For CS, this pin is active low so it will always be high during periods of inactivity by definition.

  • 0 in reply to Chuck Davenport
    Intellectual 270 points

    Chuck,

    Is the resting state of SIMO affected by pulls, or do you mean SOMI? It appears in my case that the CPU is driving the SIMO line low at idle; SOMI is controlled by the pull resistor. (CPU is master)

    And thanks for clearing this up, the SIMO line is indeed inverted in "idle state" by adjusting the polarity/phase settings. 

    Cheers,

  • 0 in reply to Jonathan Thomson
    TI__Guru 59540 points

    Hi Jonathan,

    Sorry. I got my SIMOs and SOMIs crossed. SOMI is tri-stated and thus controlled by the pull configuration. SIMO is driven low/high dependent on the phase and polarity settings.