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GPIO two buses - reason

Mikolaj Filar
Expert 1550 points

Hello all,

we have an access to GPIO by two alternative base addresses. It's a result of existence of two buses: AHB and APB. AHB is faster.


My question is:

Why the APB is provided? Do we gain something using it instead of AHB?

Best regards,

Mikolaj

  • 0
    Guru 47900 points

    Mikolaj Filar said:
    Why the APB is provided? Do we gain something

    If - as you suggest - only AHB bus was provided - might that not (predictably) lead to classic (past) bus bottleneck? 

    Might that, "independent" (and faster) data path provided by AHB - offer insight into your question?

    On the downside - I'd expect that heavy AHB usage would raise the current draw and (possibly) EMI/RFI levels of the MCU...  (we've not measured/noted such (yet) {lab testing later this summer} - that is an, "expectation" based upon experience w/other devices...)

  • 0
    Guru 92251 points

    Mikolaj Filar said:
    Why the APB is provided? Do we gain something using it instead of AHB?

    Looking at Differences Between Tiva™ C Series TM4C Microcontrollers SPMA065 shows that:

    - The TM4C123x series has GPIO ports A-J on the APB or AHB, and GPIO ports K-Q on AHB only

    - The TM4C129x series has GPIO ports A-T on AHB only

    I think having some TM4C123x series GPIO ports on APB was for software backwards compatibility, but I can't seem to find any document which states that.

  • 0 in reply to Chester Gillon
    TI__Guru**** 244400 points

    Hello Mikolaj,

    Chester is right. On TM4C123 it was software backward compatibility and on TM4C129 it was completely for performance improvement.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Expert 1550 points

    Yeah, backward compatibility was the one reason I think about but I also couldn't find this info anywhere.

    I haven't use TM4C129 family yet. I'm looking at DS of TM4C129NCPDT and on the page 54 there is a "High-Level Block Diagram" that shows that GPIOs are connected only with APB bus. Anyway, in GPIO desctription there are only AHB base addresses. Do GPIOs uses somehow an APB?

  • 0 in reply to Mikolaj Filar
    TI__Guru**** 244400 points

    Hello Mikolaj,

    The TM4C123 has AHB and APB for compatibility for LM3S devices. TM4C129 breaks away from it as all on AHB.

    Thanks for pointing out the High level Block Diagram mistake. We will correct it.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Expert 1550 points

    Thank you all for help :)

  • 0 in reply to Mikolaj Filar
    Guru 47900 points

    Applaud poster's resourcefulness in finding/presenting data correction.

    Yet - the "singularity" of the posting (and responses) concerns.  Should it not?

    Suggested earlier was the (possible) modeling/relation of Von Neumann vs. Harvard bus architecture - but applied to simpler GPIO.  If the interest is achieving higher speed GPIO - across multiple GPIO Ports (especially so during back to back access) - might such, "separate GPIO paths/methods" bear some consideration?  (thus far - here - appears not)

    And - might some ARM MCUs be moving in this direction?  (or already there?)

    Uber focus has some advantages - but perhaps "blinds" to other (especially external) valuable developments...