Unable to load address into a general purpose register whenever PLL is locked

Not sure if you guys are trying to use Halcogen, in that case pls refer to the below mentioned two functions which configures the PLL , wait for it to lock and then switch the system to use PLL clock as the source.

1. setupPLL()  /* Configure PLL control registers and enable PLLs. */

2. mapClocks() /* Wait for PLLs to start up and map clock domains to desired clock sources */

Hi Karthikeyan,

Thanks for your reply. We referred Halcogen generated code & used the above mentioned functions in our code (setup PLL & mapClocks) & also ensured that all the clock sources are valid by verifying CSVSTAT register after mapClocks function.

Issue : we are unable to load an address into a general purpose register using LDR instruction after PLL getting locked. We got this issue while emulating the code on an evaluation board.

We are able to load an address into a general purpose register before & after PLL getting locked if PLL clock is below 160 MHz (we tested it for 60, 80, 133 MHz frequencies) but an invalid address is being loaded into the register after PLL getting locked if PLL clock is 160 MHz 

Hi Karthikeyan,

I am really thankful for valuable suggestion. We have not configured the data & address wait states for flash in FRDCNTL register. We should configure the wait states as per the device datasheet for different clk frequencies