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What will be the Cortex-R4 CPSW Register MODE field when VIM Parity ISR is called?

Pashan None
Genius 5660 points

Hello Support,

During VIM RAM Parity Error, there will be ISR call based on the following register contents

Fall-Back Address Parity Error Register (FBPARERR)

Question is what will be the Cortex-R4 CPSW Register Mode field contents when the PC is pointing to FBPARERR contents?

Thank you.
Regards
Pashan

  • 0
    TI__Mastermind 49120 points

    Hello Pashan,

    The VIM parity error detection is done independent of the CPU code execution and the CPU is unaware of the VIM RAM parity error. The interrupt service routine responsible for handling the the VIM parity error case is required to address the failure in software and take the required action. The CPU mode will switch to IRQ/FIQ as per your configuration of the interrupt response to the VIM parity error in ESM (group1 channel 15).

    Regards Sunil