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TMS570LS1213 DMA MPU related questions

Libo Luo
Intellectual 940 points

Hello,

I would like to protect the DMA transactions with DMA built in MPU. For example, DMA may only read from address S, S+1, S+2, and S+3. It shall not read from any other region. It may only write the data to the address D, D+1, D+2, and D+3. It shall not write to any other region. My idea is to configure Region S as read only source region, region D as write only destination, and all other regions as no accessible (region F, starting at 0 and ending at 0xFFFFFFFF, no access).

I have done the following test on a TMS570LS1213 device.

1. Define two 32 bits words src_01 and src_02 as source. Configure MPU region 0 to start at &src_01 and end at &src_01 + 3. Configure region 0 as read only. Thus the 4 bytes (&src_01, ..., &src_01+3) are readable. Enable the MPU IRQ for region 0.

2. Define two 32 bits words dst_01 and dst_02 as destination. Configure MPU region 1 to start at &dst_01 and end at &dst_01 + 1. Configure region 1 as write  only. Thus the 2 bytes (&dst_01, &dst_01+1) are writable. Enable the MPU IRQ for region 1.

3. Configure region 3 ( the last region) to start at 0 and end at 0xFFFFFFFF. Configure region 3 as "No Access". Thus region 3 is kind of "background" region. DMA has access to only region 0 and region 1. All accesses to the addresses outside region 0 and region are not allowed.  Enable the MPU IRQ for region 3.

4. Configure DMA channel 0 to transfer 4 byte from &src_01 to &dst_01 (read element size = 1 byte, write element size = 1 byte, element count = 4, frame count = 1).

5. Start the transfer by enabling the register SWCHENA to 0x1.

I expect that a DMA MPU error will be triggered based on the following consideration: region 1 ends at &dst_01 + 1, the transfer will write 4 bytes, so DMA will try to write data to the addresses &dst_01+2, +3 which are outside the region 1 and region 0, but inside the region 3, and TRM states that

 "

If the regions defined by the start and end addresses overlap, the region defined first in the

register space determines the access privilege. For example, if region 0 and region 1

overlap, the access permissions defined for region 0 will take precedence since region 0

registers are before region 1.

"

But no error is triggered. Could you please check why no error is triggered?

 

Moreover, the register description for DMAMPR0E (TRM Section 16.3.1.60) reads that

"End Address defines the address at which the region ends. The end address usually is larger than the start address for this region; otherwise, the region will wrap around at the end of the address space."

What if the end address is equal to start address? I suppose only one byte is protected with the corresponding region, right?

Thank you and best regards,

Libo

 

  • 0
    TI__Guru**** 200256 points

    Hi Libo,

    Our DMA/MPU expert will get back to you on this soon.

    Regards,

    QJ

  • 0
    TI__Guru**** 191886 points

    Hi Libo,

      I did some experiments and my observation is that the "effective" ending address is always end_addr+3 independent of the offset "x" that is added to the end_addr, for "x" = {0,1,2,3}.

      For example, if the end_addr (the value that is programmed to the DMAMPRxE) is 0x100 or 0x101 or 0x102 or 0x103 then the "effective" ending address is actually 0x103. It looks like the MPU address compare logic is first aligning to a word address by forcing the last two address bits to zero and makes the full word address valid for the ending region.

      In your example, you have 4 elements and the end_addr is dst_01+01 then the effective ending address is dst_01+3. Therefore, these 4 byte elements all fall within the "effective" ending address of dst_01+3. However, if you have 5 elements then the fifth element would have to go to dst_01+4 and this address falls into the 3rd background region with no access and will generate a MPU violation error.

      I will submit a request to clarify the "effective" ending address in the TRM.  

  • 0 in reply to Charles Tsai
    Intellectual 940 points

    Hi Charles,

    thanks for following up the topic. I have repeated your test and seen the same behavior.

    Thanks and best regards,

    Libo