• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 608 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Forcing TMS570 phantom ISR to occur

Stojan Kovacevic
Prodigy 30 points
Other Parts Discussed in Thread: TMS570LS3137

Hello,

I am trying to force phantom ISR on TMS570LS3137, according to spna063.pdf, Scenario 1, Example 1 on page 2 and 3. But, no luck with that.

Here is what I am trying to do:

  • Instead of GIO, I am using DMA, which will be triggered when ADC conversion completes.
  • ADC is configured for 1 channel only, so there is only 1 element per frame and 1 frame per block.
  • I have DMA FTC_ISR (frame transfer complete) and BTC_ISR (block transfer complete) routines defined and enabled in VIM.
  • FTC_ISR channel is set as FIQ, while BTC_ISR is IRQ. Since there is only 1 frame per block, I expect that both ISR flags will be set at the same time, but the FTC_ISR (FIQ) will be executed first - which happens.
  • Inside FTC_ISR (FIQ) I am clearing FTC_ISR flag as well as BTC_ISR - also happens.
  • After that, I expect that instead of BTC_ISR, phantom ISR will be executed - this does not happen. BTC_ISR is also executed, and phantom ISR is not.

So, my questions are:

  1. Since spna063 is TMS470 related document, is it also valid for TMS570? I assume it is, because it is often referred to in e2e.
  2. Did anyone succeed in forcing phantom ISR on TMS570, with any ISR/FIQ combination? On purpose, not by unfortunate circumstances or bug in the code.
  3. Any ideas?

Thank you.
Regards,
Stojan

  • 0
    TI__Mastermind 22715 points

    Stojan,

    The condition for phantom interrupt to occur is that the VIM module cannot find the source of the interrupt. I am not sure how to reliably force a phantom interrupt because it is very sensitive on timing. However, I can give you an example where you may see phantom interrupt from time to time.

    (1) Configure R4 MPU to set the memory region for RTI registers as "device". Set up RTI to generate repetitive interrupts. Set up the CPU to serve the interrupt in hardware vector mode to minimize interrupt servicing delay.

    (2) The RTI interrupt flag is cleared by writing to a RTI control register. Make this instruction as the last instruction in your RTI ISR.

    (3) Since RTI control registers are configured as "device", CPU will just write the CPU store buffer and return. This may result in a condition that the RTI interrupt flag is not cleared when CPU exits ISR.

    (4) Since RTI interrupt flag is not cleared when CPU exits ISR, the same RTI interrupt will trigger IRQ. If the flag is cleared when VIM latches the interrupt later, VIM will not be able to find the source and will generate a phantom interrupt.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Prodigy 30 points

    Zhaohong,

    Thank you for the answer. It confirms that it is really difficult to produce it on purpose, because of register latching and racing conditions inside. Since there are no guaranteess, at this point we could not invest more effort into it than we already did. We are producing a software component which relies on TMS570 hardware to do its job corectly. So, we are going to trust you on this one.

    Regards,

     Stojan