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I2C Logic Low too High



I am using a TM4C123G Launchpad to interface to an Analog Devices AD7147 eval board via I2C. the Analog board provide a connector for this, so I didn't have to cut and jump anything, or anything like that. Everything was working fine with I2C 3, yesterday, but today it stopped. I eventually put a scope on the I2C lines, and found out the logic low on the clock was almost 2VDC, which is too high to be a low. I switched to I2C 0, and now it seems to be working.


This happened to me once before with the same eval kit (as in the exact same one) when interfacing to another dev board, and I believe with the same I2C 3.  In that case I had to cut some traces on the other development board (not the Tiva), and solder the wires in, and I thought maybe I somehow damaged the I2C peripheral, or GPIO. Strangely, tt later started working, which is why I was using it to talk to the Analog Devices part.


Is it possible that I damaged the I2C 3 peripheral, and it is now marginal?

What might I have done to damage it?


The initialization code is as follows, although, I don't think I have it setup wrong (since it works with I2C 0 on different pins) just the logic level on I2C 3 was wrong (twice):

   ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C3);
   ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
   
   ROM_GPIOPinConfigure(GPIO_PD0_I2C3SCL);
   ROM_GPIOPinConfigure(GPIO_PD1_I2C3SDA);
   ROM_GPIOPinTypeI2CSCL(GPIO_PORTD_BASE, GPIO_PIN_0);
   ROM_GPIOPinTypeI2C(GPIO_PORTD_BASE, GPIO_PIN_1);   

   ROM_I2CMasterInitExpClk(I2C3_BASE, SysCtlClockGet(), false);
   
 

  • Jo-Jo Smith said:
    What might I have done to damage it?

    Perhaps little - except fail to note the (likely) MCU, "pin to pin" interconnect - which iirc - impacts your PD0!  (and that's your I2C SCL line!)

    Close exam of your schematic should confirm if PD0 is among 4 pins - connected together as 2 pairs - so that your Launchpad may prove compatible with lesser MSP family.  (how delightful - that!  Connection made via 2 0-ohm jumpers - which you can (and should) properly toss!)

    If PDO is indeed among that (unfortunate pin grouping) I'd wager that its MCU "mated" interconnect is responsible for your excessive logic level - when you order SCL low.  (i.e. you have that interconnected pin set as an output - likely push pull - and its set to output a, "1."

    Should that not prove the case breaking the connections to your I2C Slave board - and monitoring that SCL line via a simple transmission - would seem valid as, "Step 2."  Recall that if your I2C pins are properly configured - they normally rely upon pull-up Rs to produce the output high.  (although new, high-speed I2C "clouds" that past standardization)  Isolate your board - isolate that pin - probe for external signals causing that unwanted signal level - before "condemning" I2C3... 

  • I just checked, and you're right, PD0 is connected to PB6 via R9, a 0 Ohm resistor.  It took me a minute to find it even once you told me.

    Thanks for the help.