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DMA Basic mode ignore XFERSIZE reaching 0x00

Luis Afonso
Guru 20670 points

Hi everyone,

I found in the datasheet the folowing in 9.2.6.2

BASIC mode can be programmed to ignore when XFERSIZE reaches 0x000 and continue copying
on request until the channel is stopped manually. If the NXTUSEBURST bit in the uDMA Channel
Control Word (DMACHCTL) register is set while in BASIC mode and the XFERSIZE reaches 0x000
and is not written back, transfers continue until the request is deasserted by the peripheral.

So if i set the XFERSIZE to 1, i should be able to do transfers over 1024 right? I need to stop it manualy right?

  • 0
    TI__Guru**** 244400 points

    Hello Luis,

    If the request gets deasserted then the uDMA will stop. So you may not be able to get the fill transfer size.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Guru 20670 points

    Hi  Amit, 

    Then i can't endlessly request a single byte DMA transfer? That only applies to various transfers as fast as it can?

  • 0 in reply to Luis Afonso
    TI__Guru**** 244400 points

    Hello Luis,

    It can be done using Scatter Gather where it can be made to initialize the Control Structure. However I do not have a working example.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Guru 20670 points

    Thank you for the info Amit,

    The DMA example you provided me before realy boosted my work with the DMA so i think i can work it out the scatter gater with some studying.

    Still, such a simple thing, transfer more than 1024 would be easy if the counter had just more than 10bits, but since it's only that size such task needs a complex task like scater-gather. Even adding a option to ignore the transfer counter and use a external periferal to count would do. Maybe sometigh to consider newer products?

    Edit:

    Maybe i was not clear. I want each transfer size to be 1 value, but i want to request a DMA transfer more than 1024 times before i need to setup the DMA transfer again with the processor

  • 0 in reply to Luis Afonso
    TI__Guru**** 244400 points

    Hello Luis,

    Adding more bits to the 10-bit is not a problem (of course would require a new device revision), but then there is no limit to do so either. However having an ignore transfer size option would be more useful, but again the issue is that it requires SRAM to store the data and would be way to complicated to just keep on adding SRAM which would serve as either the Source or Destination.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Guru 20670 points

    Hi Amit

    The ignore tranfer size would be the best  since that way it adapts to every transfer size and would not be needed to add more ram further than adding that option, at least for anytigh with XFERSIZE.

    There's always trade-offs when designing MCUs. I'm just giving a sugestion

  • 0 in reply to Luis Afonso
    TI__Guru**** 244400 points

    Hello Luis

    Suggestion noted, but I am thinking of the impact it would have on implementation. As an example, lets take that the Destination Address is a fixed Data Register while Source is a memory location set to Increment. For an infinite increment, that would mean infinite RAM, How do you propose we bind the Size of the Incrementing Location in such a case,

    On the other hand, with a fixed Transfer Size, it cannot exceed 1024 locations. The reason why I discuss this further is so that when a case is made, it has to have full pros-cons to it, analysis done before any such change is accepted.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Guru 20670 points

    Hi Amit

    Of course, this is just a way to discuss con/pros of such change and how big of a change it would actualy be in implementation.

    I don't know if we are talking about the same parameter. I was talking about the number of itens to transfer before a DMA stop is called, not the increment.