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Instruction execution time for TM4C123GH6PM

Other Parts Discussed in Thread: TM4C123GH6PM

Hi,

I'm working on Tiva C series MCU(TM4C123GH6PM). I configured the processor for 80MHz clock. Each instruction is supposed to take 12.5nSec,but  instructions are taking around 33nSec for execution on average. I have optimised the compiler for whole program optimization at level 4, speed at 5 and floating point mode strict. It will be really helpful if i get a solution for this problem.

Regards

Dilgush

  • Actualy at 80Mhz the Tiva is 100MIPS because the ARM does 1.25MIPS/Mhz.

    Are you sure your using true assembly language? try a simple ADD instruction, How are you measuring the speed of this?

  • Yes, i agree on the 100 DMIPS for the processor. I'm suing C source code and is below.

    void ADCIntHandler(void)
    {
    ADCIntClear(ADC0_BASE, 0);

    // GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, ui8PinData);

    GPIO_PORTF_DATA_R=0x02;


    FPUEnable();

    for(i=0;i<150;i++)
    {
    b[i]=c[i]=i;
    a[i]=b[i]*c[i];

    }

    // GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, 0x00);


    GPIO_PORTF_DATA_R=0x00;

    ADCIntEnable(ADC0_BASE, 0);
    }

    I'm checking the code execution time by the PORTF pin through the Oscilloscope. The output pulse goes high for 17.9uSec, which means each instruction in the for loop taking around 30nSecs.

    Please help me on this issue.

    thanks 

    Dilgush

  • The only real way to measure it is with TAL programing, I'm guessing you are seing the dissassembly and dividing the high time by the number of instructions betwen GPIO_PORTF_DATA_R right?

    I don't have any kind of scope in hand, but when i do i'll check this

  • Dilgush Idikkula said:
    . Each instruction is supposed to take 12.5nSec,but  instructions are taking around 33nSec for execution on average

    There are two issues that could cause instructions to take more than 12.5ns (1/80MHz clock):

    1) Some Cortex M4 instructions take more than one clock cycle to execute - see Cortex-M4 instructions

    2) The TM4C123GH6PM flash Prefetch Buffer may insert some wait-states when the code branches, as explained in the TM4C123GH6PM Data Sheet:

    8.2.3.1 Prefetch Buffer

    The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency is greater than 40 MHz. In this mode, the Flash memory operates at half of the system clock. The prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. The fetch buffer includes a branch speculation mechanism that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short loop branches often stay in the buffer. As a result, some branches can be executed with no wait states. Other branches incur a single wait state.