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Does WARM RESET using nRST [Open-Drain Drive] from external source will RESET PLLCTL1 and PLLCTL2 Registers?

Pashan None
Genius 5660 points


Hello Support,

nRST [Open-Drain] being driven from an external source will also reset PLLCTL1 and PLLCTL2 Register contents.

Is the above statement TRUE for TMS570 Hercules Devices?

Is the above statement TRUE for older Wega Devices [TMS470PSF761] or Delphinus Devices [TMS470PSF764]?

Thank you.
Regards
Pashan

  • 0
    TI__Guru**** 191906 points

    Hello Pashan,

      nRST is one of the system reset sources. Pulling nRST low will generate a system reset which will reset PLLCTL1 and PLLCTL2 in Hecules devices as well as the  older TMS470PSF761 and TMS470PSF764 devcies.

  • 0 in reply to Charles Tsai
    Genius 5660 points

    Hello Charles,

    I am assuming even Flash Wrapper settings will also RESET to POWER ON VALUE which is non-Pipeline Mode during nRST based RESET.

    Assume all the Flash Area is correctly programmed for either ECC [TMS570 Hercules F021] or Parity [For Wega/Delphinus F035] respectively.

     

    Assume FLASH PIPELINE is enabled always because PLL Frequency is above Threshold.

    Because nRST is asynchronous input based RESET of IC, will there be any chance to see FLASH WRAPPER Side ECC Error [For TMS570 Hercules] or PARITY Error [For Wega/Delphinus]?

    We are seeing some problem of FEDACSTATUS Register of F035 as 0x100 during continuous assertion of nRST.

    That's why I am asking this question.
    I see that in Silicon Rev A of TMS570 there was some errata related to nRST Synchronization.

    Because F035 device was before F021, so may be there is some issue with nRST Synchronization.

    Let me know if you think there might be some issue in F035 device.

    Thank you.
    Regards
    Pashan

     

  • 0 in reply to Pashan None
    TI__Guru**** 191906 points

    Hello Pashan,

      Please note that the FEDACSTATUS register is only reset by a power up reset. When you say that during continuous assertion of the nRST the FEDACSTAUS is showing 0x100, this indicates that a multi-bit error was probably detected prior to the assertion of nRST. Can you check the FUNC_ERR_ADD. What address does it indicate? Does the data at this location look suspicious against its parity? F035 device has been out on the field for a while and there is no reported nRST synchronization issue so I want to rule out this possibility for now. I assume when you enable flash pipeline mode you also set the proper wait state.

  • 0 in reply to Charles Tsai
    Genius 5660 points

    Hello Charles,

    Can you please tell me what this marked line in spnu480b.pdf TRM means?

    Thank you for the help with FEDACSTATUS related value being preserved across nRST.
    Let me see if I can find out the source of this error.
    Actually complete FLASH SPACE is correctly programmed with PARITY bits.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru**** 191906 points

    Hello Pashan,

      I think it is a typo to me. It should have said that these register bits for which indicate the sources of the uncorrectable errors should have effect on the UERR generation. The UERR is the uncorrectable error signal that is sent to the ESM module.