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RM46L430 EMIF Switching Characteristics

Other Parts Discussed in Thread: RM46L430

Hi,

We need one confirmation about RM46L430 EMIF Output Timings.

The RM46L430 datasheet pg49 "3.9 Output Timings" has the details
about the Switching Characteristics for Output Timings versus Load Capacitance(as shown below).

For Load Capacitance (CL)=15pF, the Rise time(tr) and Fall time(tf) is 2.5ns.

We would like to know if these Switching Characteristics(2.5ns for 15pF) are tested with "Zero" Load Capacitance?

For example,if we connect a memory device(with input capacitance of 15pF) to EMIF interface
then the Rise time and Fall time will be 2.5ns only?  or will it be 2.5ns + 2.5ns?

Best Regards
Prad

  • Prad,

    I believe these characteristics are based on simulation data not test data.

    CL means the load capacitance (total).   It is a lumped model and the time for one edge (rise or fall).  So 2 edges would mean 2x this.  

    This table is intended (IMO) to be used with slower peripherals like SPI or GIO and with higher loads.  EMIF isn't really  a good fit for using this simple model.  The better way to analyze EMIF is to use the IBIS model for the device.   However, we have not published a model yet for the RM46 part.

     

  • Hi Anthony,

    Thank you very much.

    Just in case our customer want's to know, with what "Load Capacitance" are
    the EMIF timings(mentioned on datasheet) are tested or simulated? is it with "Zero" load capacitance?

    It would be very helpful if there is any details of the circuit diagram of the TEST CONDITION..

    Best Regards
    Prad

  • Hi Prad,

    I believe our characterization is done by looking at the knee of the transition - where the pin just starts to show that it is transitioning - so that the result is unaffected by the load capacitance.  So in that sense you can say yes.  It's not the same but the effect is to measure and avoid the effects of capacitance.

  • Hi Anthony,

    Thank you,

    Our customer is saying that the EMIF timing Switching Characteristics is very important
    for their design, without knowing the correct timing it would be difficult to simulate the
    timings of EMIF and its related operations.

    We sincerely request you to provide us the IBIS model or simulation details of the EMIF module.
    Just in case my mail address is pradeep_kumar@ktl-corp.co.jp

    We can understand it would be difficult to provide us the simulation model,
    if possible could you please provide us the brief details of the TEST CONDITION(Circuit?) of
    EMIF timings on the datasheet.

    I am sorry for this kind of request but it seems customer is having difficulties in
    designing EMIF timings based on the datasheet.

    Best Regards.
    Prad

  • Prad,

    Sunil Oak is working on putting together the IBIS model for this chip.   We have models for the IO but you have to combine them w. the model for the package and that's the step that he is working on now.

    At the same time, the EMIF is not specified to run very fast on this part so I am actually a bit surprised that the timing is so critical.  Would you please let me know what your customer is trying to connect to?  If it is to SDRAM then I guess my concern is that most SDRAM today is spec'd to operate much much faster than the EMIF on the RM46 so there should be plenty of margin.   If it is some other memory or FPGA then they should know that the timing for the async interface supports programmable wait states for setup, strobe and hold times so it is very flexible.

    I'm assigning this to Sunil though for the IBIS portion of the question.

  • Hi Anthony,

    Thank you very much for considering the request.
    If possible please let us know the time when would we receive the IBIS model.

    Our customer seems to be connecting SDRAM and it seems this timing is crytical for their design.

    According to the datasheet 3.9 Output Timings ->Table 3-5 and your first comment
    we understood that 2.5ns (@CL=15pF) time is for low EMI pins or slower peripherals,
    so we believe, Rise time&Fall times for EMIF would be faster(i.e.<2.5ns).

    Meanwhile, I am very sorry to ask the same question again,
    regarding the "EMIF timing Switching Characteristics" on the datasheet
    as you mentioned above we understood that,the timings are based on simulation.
    Can we assume those simulations are performed without any external memory devices(Zero load capacitance)?
    (I think we may get the answer in the IBIS model)

    We appreciate your kind support.

    Best Regards
    Prad

  • Hi Prad,

    Our EMIF interface is only specified to run at 50MHz for SDRAM so this is why I don't think the rise time will be very critical.  The DRAM chips are usually designed to run 2.5x faster than this.   It would be good to make sure the customer understands this because we have two different maximum clock frequency specs for the EMIF - one for ASYNC which is 100Mhz and one for SYNC which is 50MHz.

    For practical purposes you can assume that the datasheet timings are for the no-load case.  EMIF load is probably less than 15pF so you are right it would be faster rise/fall times.  Also our spec is a max.  On average even at 15pF the rise/fall time will be faster than 2.5ns ...  you can't design to this since it *could* be 2.5ns but you would expect (say for the purposes of signal integrity) the edge rates to be faster typically maybe ~1ns.   The IBIS models include min,typ,max tables to give an idea of the variation.

  • Hi Anthony,

    Thank you very much.

    Meanwhile, please let us know if there is any updates on the IBIS model release.

    Best Regards
    Prad

  • Hi Anthony,

    I am sorry for bothering you again.

    Could you please let us know the release schedule of the IBIS Model.
    We shall ask our customer to wait till that time.

    Best Regards
    Prad

  • Hi Prad,

    The models will be on the web by the end of next week.

    Regards, Sunil

  • Hi Sunil,

    Thank you for the updates.

    Regards
    Prad

  • Hi Sunil,

    Please let me know when could we download the IBIS model.
    As you know it was not updated last week.

    Meanwhile, please let us know if there is any procedure
    to find out EMIF timings using the IBIS model.

    Regards
    Prad

  • Hi Prad,

    The files have been available for a while now and I was waiting for them to appear on the public web. I have attached the ibis model for the RM46x in the ZWT package. The official release will appear on ti.com/hercules soon.

    0044.rm46x_revb_zwt.ibs

    You can use this ibis model in a simulator such as Mentor Graphics' Hyperlynx to simulate switching of EMIF signals given some load condition.

    Regards, Sunil