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External assertion of nRST Pin and PLL synchronization

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS0432

Hello Support,

In the spruh73k.pdf for Sitara device there is a timing diagram related to External Warm Reset assertion as shown below.
Is there a similar diagram for Hercules Device Family for nRST Pin being asserted from outside world?
Can you please send me a similar timing diagram for TMS570LS0432 device?
Thank you.
Regards
Pashan

  • 0
    TI__Guru 68920 points

    Pashan,

    Our power on reset diagram is Figure 4-1 on page 26 of spns186.

    the nRST pin would be extended in duration after nPORRST is released by the timings specified in table 4-6 however there are other causes for nRST than just the nPORRST power on reset.  Theses causes are listed in Table 4-5 and can occur at any time.

    For an externally asserted reset (last entry in table 4.5) the nRST pin includes glitch filtering which is spec'd as well in table 4-6.