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RM46L430 unspecified I2C Timing spec

Other Parts Discussed in Thread: RM46L430, TCA9517

Hi,

Regarding the RM46L430 I2C I/O, there are unspecified Timing specification in the datasheet.

The I2C I/O Timing Specifications is mentioned in "Table 5-27" on the RM46L430 datasheet.

1. As you see, it has details about Setup time - tsu(SDA-SCLH) and Hold time- th(SDA-SCLL),
but we believe this timing is about I2C read and there is no details about output data delay time and
output data hold time for I2C Write. Will the these spec similar for I2C Write also?

2. Figure 5-13(below) on I2C Timings does mentions about rise and fall times tr(SCL)&tf(SCL)
but there is no actual data. Could you please let us know what is the rise and fall time for I2C?

[Edit: additional]

3. Does this "I2C I/O Timing" apply for both Master mode and Slave mode?

4. Do we have registers to change the Standard Mode and Fast Mode?


Best Regards.
Prad

  • Prad,

    The rise time for I2C we can't tell you because it depends on the bus capacitance and the external (board level) pull up resistor.  So it is determined by the board design not the MCU.

    For the fall time if you know the bus capacitance and the pull up resistor on the bus is reasonably large (K ohm) then you can get pretty close with the rise/fall time table in the datasheet.  

    The electrical spec in the datasheet for the I2C is the standard I2C bus timing spec,  and our part meets it by design and digitally as long as you program the clock prescaler between 6.7MHz and 13.3MHz as it says in the TRM chapters 30.1.3 Clock Generation  and 30.4.3 "Prescaler" in the I2C section.   This is because we use the internal clock which is so much faster than the bus to generate the timings.  The actual A/C delays from clock to pin are negligable. And in fact on inputs we have a noise filter to supress any glitch faster than 50ns which is slower than any clock to IO pin delay.

    You can control the I2C clock frequency by using the registers described in 30.1.3.  The minimum high and low time on the SCL clock is programmable.  Please make note of the comment that you will actually run slower than you program the bus because of external pull up delays and synchronization delays (slave can slow the clock down dynamically on the I2C bus...)    If the transfers are throughput critical I2C isn't the right bus to use - look at SPI instead.

  • Hi Anthony,

    Thank you so much for the information.
    We understood the I2C is as per the I2C Spec(v2.1).

    The problem is our customer is using I2C level translater IC(TCA9517)
    between the Master(RM46x) and the slave.

    And the I2C level translater IC has its own Propagation delay and transition time.
    So we are worried that even though the Master(RM46x) outputs data according to the
    specification, because of the translater IC's delay, these outputs may not
    be according to the slave spec,

    so it would be helpful if we know the below timings.

    SDA falling edge to SCL clock HIGH"hold time for Start Condition
    SCL clock rising edge to SDA HIGH hold time for Stop Condition
    (time between the SCL clock rising edge to SDA bus free)

    Best Regards
    Prad

  • Hi Prad,

    Ok makes sense.  Unfortunately the only data that we have on this is in the datasheet.

    I would guess that out of the range of clock frequencies in the spec for the I2C SCLK internally if the customer picks the mid value they should get timings that are balanced between the setup and hold time limits of the I2C spec leaving the most margin to the bus spec for an additional external delay that operates in both directions.

    However, the conservative approach would be to back down on the clock frequency as a way to increase margins.

  • Thank you..

    Your support is very helpful for our customer's design.

    Regards
    prad