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Performance Monitor Unit and RTI on TMS570LS3137ZWT

Gael Le Moing
Expert 1020 points

Hi,

I am considering the possible solutions for time measurement on TMS570LS3137ZWT microcontroller.

1- Using RTI: I can configure a counter that increments the Free Running counter each time it overflows, then I can have a VCLK tick counter on 64 bits.

Pros:

  - Counter on 64 bits

  - Registers writeable only in Privileged mode, and read-accessible in User mode

Cons:

  - Counting VCLK ticks instead of GCLK ticks.

  - I guess the access time is bigger than using the PMU (access through the Peripheral Central Resource Bridge)

2- Using PMU: I can enable the Cycle counter and count the GCLK ticks with it.

Pros:

  - Counting GCLK bits (more accurate for time measurement)

  - I guess the access time is better since the PMU is in the core

Cons:

  - Cycle Counter Register is only a 32 bits counter (max value corresponds to something like 26 seconds if the CPU runs at 180MHz).

  - The documentation indicates that the registers are not accessible (at all...?) for User mode. If I want the User mode can access to them, I have to enable the user access (via the User Enable Register of the PMU) but this gives more than only a read-access for user-mode, and this can not be allowed for our critical system.

Finally, here are my questions: do I understand correctly the documentation about the user access for PMU registers or is there a way to configure only a read-access for User mode on these registers (writeable only in privileged mode)?

How can I simulate a 64 bits counter for GCLK ticks with the PMU (without interruptions if possible)?

Thanks to everyone for your help.

Gael

  • 0
    TI__Mastermind 23000 points

    Hi Gael,

    The access time differences in accessing the PMU vs. the RTI are primarily a problem when trying to evaluate very small time intervals.  If you are looking at large time intervals and need a 64b counter, the ~30-100 cycles of difference introduced by the interconnect on each timer access may not be critical to your application.

    If you can live with a 64 clock minimum granularity, you can set the "D" bit in the Performance Monitor Control Register and this will effectively extend the cycle counter beyond 32b by only counting every 64th clock cycle.

    I do not believe the ARM hardware allows read vs. write access differentiation in PMU register accesses for user mode once the USEREN bit is enabled.

    Regards,

    Karl