DMA - unable to use Working Control Packets

This post belongs in the "Hercules Safety Microcontrollers" forum, I believe, so I am moving it.

Marco,

Can you specify which device and hardware board you are using?

My apologies, I completely forgot to specify the most important detail about the problem.

The device I'm using is

     TMS570 Microcontroller USB Kit  (http://www.ti.com/tool/tmdx570ls20susb)

Thanks,

     Marco

Hello Marco,

   I'm not too sure what you are trying to do to monitor the two DMA channels by reading the PBACSADDR, PBACDADDR, and PBACTC. Are you trying to find out when each channel will finish its transfer? There are various ways the DMA can generate interrupt to the CPU when certain amount of data is transferred. For example, you can program the DMA to interrupt the CPU when half of the specified transfer count is transferred or the entire specified amount of data is transferred. Or you don't want to use  interrupt mode but rather polling? If you want to poll the status of the channels you can still read the various interrupt status registers such as FTCFLAG, LFSFLAG, HBCFLAG and BTCFLAG.

  Let me know explain how the working control packet works. There is the primary control packet which stores the channel information of each channel. As the DMA works on the channels, it needs to save the current context of each channel in the working control packet. The working control packets are stored in the local DMA memory. They are memory mapped. You can view all the working control packets at address starting at 0xFFF80800. The working control packet for channel 0 starts at 0xFFF80800 and the working control packet for channel 1 will start at 0xFFF80810. In the working control packet you can find the current source address, destination address and transfer count. Note that the working control packet is only updated when a channel is arbitrated out. If you have two channels and configure them in round-robin arbitration then the DMA will make some transfers for channel 0 and arbitrates to channel 1 in a round robin fashion. Each time the channel is arbitrated out, its context is saved in the working control packet. Therefore, the source/dest addr and transfer count stored in the WCP will be aligned to an arbitration boundary. Let's say each channel has 16 elements per frame and you are using 8-bit transfer size. After 4 elements for channel 0 is transfered, the DMA will switch to channel 1. It will save 12 as the transfer count in the WCP for channel 0 so that later when it switches back to channel 0 it knows that there are still 12 elements left to transfer. The PBACSADDR/PBACDADDR/PBACTC shows the current runtime value of the addresses and transfer count of the active channel. If channel 0 is the current active channel being processed by the DMA, then these registers may show the transfer count as 15, 14, 13 or 12. It depends when the CPU is reading the registers.

Thank you very much Charles for your answer.

In my first post, I didn't explane properly.

I used PBACSADDR/PBACDADDR/PBACTC just as first test to monitor one DMA channel (and they worked fine).

Then when I tried to monitor two channels, in accordance with TRM (an with what you explained in your post), I decided to use WCP in order to monitor DMA transfer completion for each channel.

The problem is that I cannot see any change in WCPs, for any channel: they are always freezed to the initial value and they don't change even if I know that destination buffers are filled.

I hope I better explained my point.

    Marco

Hi Marco,

  Can you please tell me the arbitration scheme you configure? By default after reset the arbitration scheme is "fixed". Please check the Port Control Register. If they are "fixed" then please change to "round-robin". When you have fixed scheme it means the channel 0 will always have higher priority than channel 1. The DMA will transfer all the elements asked by channel 0 before it switches to channel 1. There is nothing to save to the working control packet as there is no need to save the context of each channel. Note that I said in the last reply that DMA will save the context of each channel to the WCP when the DMA needs to switch to a different channel due to "round-robin" scheme.

  I still believe that the best way to monitor the completion of a channel transfer is to either poll the vaious status flags or via the interrupt. I want to give an example where the WCP may not indicate the completion of transfer.

  Let's say you change the priority scheme to round-robin. Yes, you will see the WCP being updated with the latest transfer count, source/dest addresses of each channel. Let the example be that both channels will have 16 elements per frame and each channel is setup for 8-bit transfer. The DMA will arbitrate between the two channels for every 4 elements it transfers. There will come time when both channel 0 and 1 have only 4 elements left to transfer. In the final round, the DMA will transfer the remaining 4 elements of channel 0. However, it will NOT update the WCP by writing 0 element. The reason is that it has completed all the transfers for channel 0. There is no more context to save for channel 0. The DMA will then switch to channel 1 by reading the latest context for channel 1 from the WCP and transfer the remaining 4 elements of channel 1. Again, once the DMA is done with channel 1 it will NOT update the WCP. So if you try to monitor the DMA channels by reading the WCP they will never indicate 0 transfer count left. It will indicate 4 in the element count field. The DMA will update the various status flags to indicate its progress. This is a reliable way to know when a channel is complete.