C129 Partial Host Bus

Hello Rob,

Can you please let us know which data sheet, section and page you are referring for "Partial Host Bus"? I did a search of the key word "partial" in the EPI section of the data sheet and it did not turn up (so want to be sure we are looking at the same data sheet)

Regards

Amit

Amit,

Thanks for your assistance.

If you look at the block diagram on the User's Guide for the TIVA C129x LCD Development Board, page 7 [SPMU360], it shows the EPI connector as an "EPI Partial Host Bus 16/8".   We would like to do some communications development on the C129 and may choose to add some external SRAM [perhaps 2 Mbits].   I would like to know how difficult that may be.

Thanks,

Rob

Hello Rob

Thanks for the context. The partial Host Bus means that not all EPI pins are on the header. The EPI module has 36 pins while on the DK-TM4C129 not all pins are available on the two Jumper Headers of J27 and J28.

The Figure 11-11 of TM4C129XNCZAD shows how to interface the SRAM CY62147 to the device. It does not show the Address Latch logic which uses ALE on EPIS030 pin as the control signal.

So in essence the DK-TM4C129 "Partial" EPI can be used to connect an external SRAM.

Regards

Amit

Thank you, Amit.  Next questions regarding the partial bus: 

How many address lines are on the partial bus, and are they mux'ed?  (Alternately, how much address space do devices have off of the partial bus?) 

Also, what bandwidth can we expect between the processor and SRAM on this bus, assuming the minimum number of wait states?

Finally, are there any restrictions on SRAM accessed through the partial bus?  (e.g., can code execute out of SRAM off of the bus?  Doubtful we would need to do that but would like to know going in.)

Regards,

Tim

Hello Tim,

The Host Bus Mode provides for upto 512MB of addressing. However as mentioned this is possible in Address Data Mux mode and would require a Latch externally if the same does not exist in the memory device.

The max operating frequency of the TM4C129 is 120MHz with EPI maximum output clock being 60MHz on the IO side. Why I do not say it to be half of system clock is because if the System Clock is 60MHz the EPI can also work at 60MHz.

Generally there is no restriction on code execution from EPI. However there are two known issues (please see the errata) for LCD + CPU + EPI.

Regards

Amit

Hello Amit,

Thank you again for the information.  We are also considering SDRAM vs SRAM for the EPI. 

Is there a reference design for the C129 that uses SDRAM off of EPI?  Are there recommended SDRAM components?  We would be interested in a relatively small SDRAM, say 8 megabytes or so.

Thanks once more,

Tim

Tim Cooper1 said:

Is there a reference design for the C129 that uses SDRAM off of EPI?  Are there recommended SDRAM components? 

 Hi, I think this one is complete reference and for a slight few more dollar than DK you can get a complete dev kit:

http://www.mikroe.com/mikromedia/5/tiva/

 IMHO is better just wait to have TM silicon on board than XM.