The configuration of the main PLL and clock wrapper is controlled by two registers, PLLCTL1 (offset 0x70) and PLLCTL2 (offset 0x74) in the System module. Programming these two registers selects the operating mode, frequency, reset behavior on PLL slip or oscillator fail.
.
PLLCTL1 register fields are used for control frequency and reset behavior on PLL slip or oscillator fail.
PLLCTL2 register is dedicated to frequency modulation.
When configuring the PLL, care should be taken to program all PLL/wrapper related fields correctly before enabling it.
The details of these registers, a programmation example, and details on the F035 FMzPLL calculator tool can all be found in the Clock Module Chapter of the TMS570LS series Technical Reference Manual SPNU489.
For an easier way to calculate the PLL control register settings using the F035 FMzPLL calculator follow this post:
http://e2e.ti.com/support/microcontrollers/tms570/f/312/t/36777.aspx
