TMS570LS3137 - SPI and DMA

Milan Petrzilka

Other Parts Discussed in Thread: TMS570LS3137

Hello. I am developing diploma thesis with TMS570LS3137. I need to configure SPI4 peripherial (NOT mibSPI) to send 16 uint16 data words. I have sucessfully configured SCI with DMA and this seems to be not the same. Polling method works - all words I want to are sent. But, the DMA does not work.

SPI dataconfig set before. DMA enabled before. SPI data transfer with polling method before this ok.

/* Configure DMA for transfer */
   g_dmaCTRLPKT_A4960Tx.SADD      = (uint32) &A4960reg[0][0]; /* source address             */
   g_dmaCTRLPKT_A4960Tx.DADD      = (uint32) &spiREG4->DAT1;    /* destination address       */
   g_dmaCTRLPKT_A4960Tx.CHCTRL    = 0;                 /* channel control            */
   g_dmaCTRLPKT_A4960Tx.FRCNT     = 1;                 /* frame count                */
   g_dmaCTRLPKT_A4960Tx.ELCNT     = 16;               /* element count              */
   g_dmaCTRLPKT_A4960Tx.ELDOFFSET = 4;                 /* element destination offset */
   g_dmaCTRLPKT_A4960Tx.ELSOFFSET = 0;                 /* element source offset */
   g_dmaCTRLPKT_A4960Tx.FRDOFFSET = 0;                 /* frame destination offset   */
   g_dmaCTRLPKT_A4960Tx.FRSOFFSET = 0;                 /* frame source offset   */
   g_dmaCTRLPKT_A4960Tx.PORTASGN = 4;                 /* port b                     */
   g_dmaCTRLPKT_A4960Tx.RDSIZE    = ACCESS_16_BIT;     /* read size                  */
   g_dmaCTRLPKT_A4960Tx.WRSIZE    = ACCESS_16_BIT;     /* write size                 */
   g_dmaCTRLPKT_A4960Tx.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
   g_dmaCTRLPKT_A4960Tx.ADDMODERD = ADDR_INC1;         /* address mode read          */
   g_dmaCTRLPKT_A4960Tx.ADDMODEWR = ADDR_FIXED;         /* address mode write         */
   g_dmaCTRLPKT_A4960Tx.AUTOINIT = AUTOINIT_OFF;      /* autoinit                   */

    dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT_A4960Tx);
    dmaReqAssign(DMA_CH1, 25U);
    dmaEnableInterrupt(DMA_CH1, FTC);
   dmaSetChEnable(DMA_CH1, DMA_HW);

    spiREG4->INT0 = (1<<16);

I have a few questions.

1. What the "element destination offset means"? Is this good for offset in the destination memory, for example SPI Tx buffer DAT1 consist of CSHOLD, WDEL, CFSEL, CSNR, and TXDATA [15..0]. With the respect of endianity (big endian) the data word uint16 should be written to address not &spiREG4->DAT1, but .. which? And is the value number of bits, bytes, or the WRSIZE? Or am I wrong?

2. DMA enable. spnu499b, page 554: "DMA enable bit. The configuration registers and channel control packets should be setup
first before DMA_EN bit is set to one to prevent state machines from carrying out bus
transactions. If DMA_EN bit is cleared in the middle of an bus transaction, the state
machine will stop at an arbitration boundary."

I can't imagine, that I will have to "pause or stop" all dma transfers in application to reconfigure one control packet.

Please help.

Thanks

Milan

over 11 years ago

0 Charles Tsai over 11 years ago

TI__Guru**** 191486 points

Hello Milan,

Your current setup (16bit WRSIZE and FIXED address) will only write to the upper 16bit (CSHOLD, WDEL, DFSEL and CSNR) of the DAT1 register. The offset you use has not effect since you configure the destination addressing mode to be FIXED. DMA operates in big endianism mode. Your destination address is &spiREG4->DAT1 so the DMA will write to the upper 16bits only.

I will suggest to use FIXED addressing mode for the destination but change the WRSIZE to ACCESS_32_BIT. This way the DMA will read two 16-bit data with each containing control info such as CSHOLD, CSNR and etc and the other containing the 16bit TXDATA from the source buffer and write one 32-bit data to the DAT1.

For your second question, it merely how the DMA will behave when the DMA is disabled in the middle of a transaction. The DMA needs to wait for some boundary to terminate the transaction instead of abruptingly kill the transaction which can lead to the bus protocol violation. If you have no intention to disable the DMA in the middle you will be fine.