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Overlapping DMA destinations for two channels

nick foster
Prodigy 30 points

Other Parts Discussed in Thread: TM4C123GH6PM

Hi,

I'm using the TM4C123GH6PM to gather quadrature baseband data on ADC0 and ADC1 simultaneously using the ping-pong buffering mode. It's all working fine. However, to simplify processing and to keep memory accesses more local, it would be helpful to have the samples ordered as complex int16 data -- e.g., I, Q, I, Q, I, Q....rather than two buffers of I, I, I... and Q, Q, Q....

To do this, I set up the DMA transfers for ADC0 and ADC1 such that ADC0 writes to buffer[0], and ADC1 writes to buffer[1]. Then I changed the DMA destination increment parameter for ADC0 and ADC1 to 32 bits instead of 16 bits. This whole thing appears to work just fine, except now the first ADC0 sample of every transfer is 0, rather than the actual sample.

Any suggestions as to why this is so would be appreciated, as would an explanation as to why what I'm trying to do is insane or impossible.

Best,

Nick

  • 0
    Guru 47900 points

    Bravo on both your inventive application method and your clear - yet concise - description.

    Strange (to my feeble mind) that only the first sample - and only on ADC0 - is impacted.  Might you switch the order of your transfer mechanism - and note if the issue then moves to ADC1? 

    Seemed possible that your switch from 16 to 32 bits caused/contributed - yet that's doubtful due to the seeming success of all remaining 32 bit transfers.

    Perhaps a delay - just prior to the very first DMA transfer - may reduce or correct?  And - one wonders if that "0 value" resulted from a valid uDMA transfer - or was already resident (that location) or signals some form of corruption which is subsequently arrested?

  • 0
    TI__Guru**** 244440 points

    Hello Nick,

    Thanks for a great post (very clear information) on what you are trying to do. Is the Data Size set to 32 or 16?

    Also when you mention that the first ADC0 sample of every transfer is 0 then instead of the 32-bit word being

    IQ

    IQ

    IQ

    does it appear as

    0Q

    0Q

    0Q

    If I=ADC0 data and Q=ADC1 data?

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Prodigy 30 points

    Thanks for the reply, Amit.

    Is the Data Size set to 32 or 16?

    The data size is 16 bits.

    Also when you mention that the first ADC0 sample of every transfer is 0 then instead of the 32-bit word being

    IQ

    IQ

    IQ

    does it appear as

    0Q

    0Q

    0Q

    If I=ADC0 data and Q=ADC1 data?

    Even more strangely, it shows up as:

    0 Q I Q I Q I Q....

    Only the first I sample of the buffer is set to zero. Even *more* strangely, this only appears using the primary DMA structure. I'm using contiguous buffers for both DMA transactions, with the PONG buffer (or alternate DMA transfer destination) following the PING buffer:

    buffer = [PING<256 elements>   PONG<256 elements>]

    ...the first I element of PONG is correct, while the first I element of PING is not.

    Strange!

    Nick

  • 0 in reply to nick foster
    Guru 47900 points

    NewzFlash:  famed poster cb1 departs (hangs himself)...  (oh well...)

  • 0 in reply to nick foster
    Prodigy 30 points

    Let's get stranger, while we're here. The sample is not set to zero; it's simply not ever written. My data actually looks like: 0IQIQIQ... -- it's offset by one element. Likewise, it writes off the end of the buffer one element.

    I can get it to work if I offset the destination address of all the DMA transfers by -1. I'm assuming this has to do with the memory alignment of the DMA transfer, but I can't immediately see how.

    Nick

  • 0 in reply to nick foster
    TI__Guru**** 244440 points

    Hello Nick,

    If you can share the code, then I can try the same and see what the issue is? If I do the code then it will take me a couple of days.

    Also can you try to reset the ADC's and uDMA before the SysCtlPeripheralEnable is called? The API call to reset the peripheral is SysCtlPeripheralReset. The reason why I say so is that the pattern changed and could it be a false DMA request from the previous run?

    Regards

    Amit