SSI (SPI) Frame End signal not occurring

Hello Jrmymllr,

The code seems all fine except that you are using the READ_WRITE mode and not clearing the Read FIFO. Also instead of Non Blocking can you replace it with Blocking function, as I suspect the FIFO is not getting written with the end of frame,

Regards

Amit

Amit Ashara said:

Hello Jrmymllr,

The code seems all fine except that you are using the READ_WRITE mode and not clearing the Read FIFO. Also instead of Non Blocking can you replace it with Blocking function, as I suspect the FIFO is not getting written with the end of frame,

Regards

Amit

uint32_t x;
g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 48000000);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0XDAT0);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2);
SSIConfigSetExpClk(SSI0_BASE, 48000000, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 16);
SSIAdvModeSet(SSI0_BASE, SSI_ADV_MODE_READ_WRITE);
SSIAdvFrameHoldEnable(SSI0_BASE);
SSIEnable(SSI0_BASE);
SSIDataPut(SSI0_BASE, 0x1111);
SSIDataPut(SSI0_BASE, 0x2222);
SSIDataPut(SSI0_BASE, 0x3333);
SSIAdvDataPutFrameEnd(SSI0_BASE, 0x4444);

SSIDataGet(SSI0_BASE, &x);
SSIDataGet(SSI0_BASE, &x);
SSIDataGet(SSI0_BASE, &x);
SSIDataGet(SSI0_BASE, &x);
SSIDataGet(SSI0_BASE, &x);
SSIDataGet(SSI0_BASE, &x);

Hello Jrmymllr,,

That is strange since I used the Advanced Mode to access the Macronix Flash on the DK-TM4C129 recently and it worked. I will try to get a simple code out for you in which the FSS comes back high at the end of transmission

Regards

Amit

Amit Ashara said:

Hello Jrmymllr,,

That is strange since I used the Advanced Mode to access the Macronix Flash on the DK-TM4C129 recently and it worked. I will try to get a simple code out for you in which the FSS comes back high at the end of transmission

Regards

Amit

Great thank you.

We note that both code listings avoid, "GPIOPinConfigure()" for GPIO_PA5.   Is that deliberate - and if so - correct?

There's imprecision both w/in your report, "you send more than 16 bits" and Amit's use of, "Advanced Mode to transact w/a memory device."  (number of bits - hopefully in excess of 16 (to match Jeremy's post) was not disclosed) 

Thus - would it not prove useful to confine (temporarily) your transmission to 16 bits - and see if that works?   And - would be useful if Amit could (somewhat) detail number of bits in his past operation.  (may have been too far past to be readily recalled)  Such (real) detail always helpful...

While a long-shot - might some (past) code blurb have escaped recent note - and it disrupts the expected/desired FSS toggle?

cb1_mobile said:

We note that both code listings avoid, "GPIOPinConfigure()" for GPIO_PA5.   Is that deliberate - and if so - correct?

There's imprecision both w/in your report, "you send more than 16 bits" and Amit's use of, "Advanced Mode to transact w/a memory device."  (number of bits - hopefully in excess of 16 (to match Jeremy's post) was not disclosed) 

Thus - would it not prove useful to confine (temporarily) your transmission to 16 bits - and see if that works?   And - would be useful if Amit could (somewhat) detail number of bits in his past operation.  (may have been too far past to be readily recalled)  Such (real) detail always helpful...

While a long-shot - might some (past) code blurb have escaped recent note - and it disrupts the expected/desired FSS toggle?

PA5 is likely left over from a TI example code listing, and I'm not using it right now.  

Just now I tried commenting out all SSIDataPut(), leaving only the SSIAdvDataPutFrameEnd().  FSS still doesn't jump high after transmission. 

I'm at a loss as to why FSS doesn't behave as it seems it should.  This characteristic is a bit confusing as it is.  For example, the datasheet states:

"When data is first written to the TX FIFO, a SSInFss is asserted low indicating the start of a frame.  At the end of transmission, bit 12 of the last data entry in the TX FIFO signifies whether a a frame is ending."

Am I missing something, or is this just bizarre?  Why is a bit in the TX FIFO determining if the frame is ending?  Surely I'm overlooking something. 

In any case, I'm using the TivaWare function so I don't directly deal with registers, but still at times like this I consult the datasheet.

Petrei said:

Hi,

I have also a question. Here it is what is stated in driverlib documentation (source code):

//! When using an advanced mode of operation, the SSI module must have been
//! configured for eight data bits and the \b SSI_FRF_MOTO_MODE_0 protocol.
//! The advanced mode operation that is selected applies only to data newly
//! written into the FIFO; the data that is already present in the FIFO is
//! handled using the advanced mode of operation in effect when that data was
//! written.

Now - for advanced mode should have only eight bits transmitted, but in this case which one is the bit 12 of the last data entry in the TX FIFO ? (as stated in the user manual).

Regards,

Petrei