Warning in Halcogen mibspi

David Sabol

Other Parts Discussed in Thread: HALCOGEN, TMS570LS0332

Hi,

Just an FYI. As I am working with mibspi, I noticed a warning is being generated after enabling the mibspi driver. I am using the TMS570LS0332, CCS 6 and Halcogen 4.1. Hopefully this can be addressed in the next release.

The warning is "#188-D pointless comparison of unsigned integer with zero", the code is in mibspiInit

#if (1U > 0U)
        {
            while (i < (1U-1U))
            {
                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
                                          | (uint16)((uint16)1U << 10U)  /* enable WDELAY */
                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
                                          | (uint16)((uint16)0U << 8U)  /* data format */
										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */
                i++;
            }

Thanks,

David

over 11 years ago

0 Sunil Oak over 10 years ago

TI__Mastermind 49120 points

Hi David,

I am forwarding this query to the HALCoGen team for their comment.

Regards, Sunil

0 Prathap over 10 years ago

TI__Genius 14205 points

Hi David,

MIBSPI driver is generated by template based on the GUI configurations with assumption that Transfer group length would be more than 2. In that case the warning will not appear.

I see you have configured TG of length 1, Is there a reason for not using the compatibility mode( regular SPI mode) since you are using only one MIBSPI buffers which is equivalent to compatibility mode.

Ideally MIBSPI will be used with Transfer group with buffers of length more than 3 to make use of the buffer implementation.

0 David Sabol over 10 years ago in reply to Prathap

Genius 4850 points

I have switched over to compatibility mode, but the reason I was using mibspi with a transfer group size of 1 is because I am interfacing with the TPS65381 using the TI TPS Driver, and a transfer group size of 1 is specified in the wiki below

http://processors.wiki.ti.com/index.php/Configuring_HALCoGen_for_using_TPS_Driver

0 Prathap over 10 years ago in reply to David Sabol

TI__Genius 14205 points

Hi David,

I think it is right move to use compatibilty mode to reduce code size and RAM dependency for a Single buffer data..

I checked with the TPS Wiki author, he mentioned that he was comfortable with MIBSPI and hence used it.
He also mentioned that it is up to the TPS driver user to implement the "send_recieve_data"

0 Vladimir Romanov over 9 years ago in reply to Sunil Oak

Intellectual 940 points

Hi!

I also have this annoying warning.

Please fix Halcogen templates. Bellow I suggest way to fix template. Changes marked with //<!===============

    /** - initialize buffer ram */
    {
        i = 0U;

#if (%%MIBSPI1:MIBSPI1_TG0_LENGTH%%U > 0U)
        {
#if (%%MIBSPI1:MIBSPI1_TG0_LENGTH%%U > 1U) //<!===============
            while (i < (%%MIBSPI1:MIBSPI1_TG0_LENGTH%%U-1U))
            {
                mibspiRAM1->tx[i].control = (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_MODE%%U << 13U)  /* buffer mode */
                                          | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_CSHOLD%%U << 12U)  /* chip select hold */
                                          | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_WDEL%%U << 10U)  /* enable WDELAY */
                                          | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_LOCK%%U << 11U)  /* lock transmission */
                                          | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_DFSEL%%U << 8U)  /* data format */
#if %%MIBSPI1:MIBSPI1_TG0_USE_CS_ENCODE%%
                                          | ((uint16)(~((uint16)%%MIBSPI1:MIBSPI1_CSDEF%%U ^ (uint16)%%MIBSPI1:MIBSPI1_TG0_CS_ENCODE%%U)) & (uint16)0x00FFU);  /* chip select */
#else
                                          | ((uint16)(~((uint16)%%MIBSPI1:MIBSPI1_CSDEF%%U ^ (uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_CSNR%%)) & (uint16)0x00FFU);  /* chip select */
#endif
                i++;
            }
#endif //<!===============
            mibspiRAM1->tx[i].control = (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_MODE%%U << 13U)  /* buffer mode */
                                      | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_CSHOLD_LASTBUF%%U << 12U) /* chip select hold must be zero for last buffer */
                                      | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_WDEL%%U << 10U)  /* enable WDELAY */
                                      | (uint16)((uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_DFSEL%%U << 8U)  /* data format */
#if %%MIBSPI1:MIBSPI1_TG0_USE_CS_ENCODE%%
                                      | ((uint16)(~((uint16)%%MIBSPI1:MIBSPI1_CSDEF%%U ^ (uint16)%%MIBSPI1:MIBSPI1_TG0_CS_ENCODE%%U)) & (uint16)0x00FFU);  /* chip select */
#else
                                      | ((uint16)(~((uint16)%%MIBSPI1:MIBSPI1_CSDEF%%U ^ (uint16)%%MIBSPI1:MIBSPI1_TG0_BUF_CSNR%%)) & (uint16)0x00FFU);  /* chip select */
#endif


            i++;
        }
#endif