• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 29 subscribers
  • Views 1449 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ESM Testing?

Matt Harding
Prodigy 220 points
Other Parts Discussed in Thread: HALCOGEN

I am using RM48 with CCS6 and Halcogen 4.

I am working to set up proper ESM responses for the various condiitons. For example, first, I want to enable a low level interrupt on DCAN1 parity error (Channel 21). In this interrupt, I want to simply increment a counter of parity errors.

I set these conditions in Halcogen, but I'm not sure how to correlate that setup to the code. It looks like when a parity error occurs on DCAN1, it should enter esmLowInterrupt() in esm.c. This will call esmGroup1Notification() in notification.c, and this is where I put some user code to increment my counter.

Is that assessment true? And how can I test my setup, i.e. is there a way, via software, to simulate a parity error in DCAN1, or the other various errors that the ESM can detect?

Thanks,

Matt

  • 0
    TI__Mastermind 49120 points

    Matt,

    HALCoGen does generate routines to verify parity error generation from DCAN1 RAM. You can choose to generate this code by "checking" the right boxes on the "SAFETY INIT" tab. See pic below.

    HALCoGen will then generate a C-file called sys_selftest.c and will include diagnostic routines for all safety features selected via the GUI. For example, DCAN1 RAM parity check routine looks like this:

    void can1ParityCheck(void)
{
    volatile uint32 canread = 0U;
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
    uint32 canctl_bk =  canREG1->CTL;

/* USER CODE BEGIN (65) */
/* USER CODE END */

    /* Disable parity, init mode, TEST mode */
    canREG1->CTL = 0x00001481U;

    /* Enable RAM Direct Access mode */
    canREG1->TEST = 0x00000200U;

    /* flip the parity bit */
    canPARRAM1 ^= 0x00001000U;

    /* Enable parity, disable init, still TEST mode */
    canREG1->CTL = 0x00002880U;

    /* Read location with parity error */
    canread = canRAM1;

    /* check if ESM group1 channel 21 is flagged */
    if ((esmREG->SR1[0U] & 0x00200000U) == 0U)
    {
        /* No DCAN1 RAM parity error was flagged to ESM */
        selftestFailNotification(CAN1PARITYCHECK_FAIL1);
    }
    else
    {
        /* clear ESM group1 channel 21 flag */
        esmREG->SR1[0U] = 0x00200000U;

        /* Disable parity, init mode, TEST mode */
        canREG1->CTL = 0x00001481U;

        /* Revert back to correct data, flip bit 0 of the parity location */
        canPARRAM1 ^= 0x00001000U;
    }

    /* Disable RAM Direct Access mode */
    canREG1->TEST = 0x00000000U;

    /* Restore CTL register */
    canREG1->CTL = canctl_bk;

    /* Read Error and Status register to clear Parity Error bit */
    canread = canREG1->ES;

/* USER CODE BEGIN (66) */
/* USER CODE END */
}

    As you can see, this parity check is done in software by introducing a parity error and then reading the corresponding DCAN RAM location. The routine also checks to ensure that the correct ESM flags are getting set.

    You can modify your start-up routine to enable ESM interrupt generation for group1 channel 21 to verify that an interrupt request is actually generated. Note that you need to unmask the corresponding interrupt channel in the VIM and also enable global interrupt exception handling in the CPU (clear 'I' bit in CPSR).

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 220 points

    Thank you for the help Sunil. I see now where that test occurs.

    I did enable ESM interrupt generation, and the interrupt did occur, as expected. However, the esmLowInterrupt clears the bit in ESMSR, thus the self test fails. This can be worked around without too much difficulty.

    Thanks,

    Matt