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EPI bus reads

George Cranshaw
Prodigy 20 points
Other Parts Discussed in Thread: TM4C129DNCPDT

Hi all

I have an EPI bus interface to a FPGA.  EPI is configured to run in GP mode.

in the tm4c129dncpdt manual on page 852 there is figure 11-21 which seems to indicate there is a

burst read mode where the reads after the first read all take one clock.  we are using 8 data bits and 4 address bits.

When I try to read more than one byte using either blocking reads(LDRH from mapped memory) or non blocking reads using registers and FIFO I get two clock cycles for each byte read.

I would have expected 3 clock cycles to read two byte 1: address readstrobe hi, 2: data0, new address 3: data1.

Is this possible? is the figure wrong? how do I "burst read" if it is possible?

Thanks

  • 0
    TI__Guru**** 244400 points

    Hello George

    I checked the GP Mode of operation and it seems that you are correct and this may be an error in the figure. If you can share the EPI Configuration, it would be more helpful to check it against a specific configuration

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Prodigy 20 points

    EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);
    *((volatile uint32_t*)EPI0_BASE) |= 0x100; /* enable integer divider mode */
    EPIDividerSet(EPI0_BASE, 2); /* 50MHz */
    EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_20 |
    EPI_GPMODE_DSIZE_8, 0, 0); /* Frame size 0 */
    EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_16MB | EPI_ADDR_PER_BASE_A |
    EPI_ADDR_RAM_BASE_NONE | EPI_ADDR_CODE_BASE_NONE);

    all other values are default/reset values

  • 0 in reply to George Cranshaw
    TI__Guru**** 244400 points

    Hello George,

    Thanks for the code. I can confirm that the Figure is not correct. There would be a delay between two consecutive reads.

    Regards

    Amit

  • 0 in reply to Amit Ashara
    Intellectual 390 points

    I have the same issue , 2 CPU clock after each read with different configuration (16 bit data , 12 bit address):

     // EPI_FPGA_CONFIG = (EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_DSIZE_16)

     EPIDividerSet(EPI0_BASE, 4);

     EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

    EPIConfigGPModeSet(EPI0_BASE, EPI_FPGA_CONFIG, 0, 0); 

    EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_64KB | EPI_ADDR_RAM_BASE_6);

    When I read 16 or 32 bit from the EPI , I get after each read, two additional CPU clock.

    for write I get burst of write.

    Is it Bug in the Chip ?

    thx