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RM48 DCAN IF3 DMA block transfer

C-Li
Prodigy 175 points

Hello,

I am using 32 mailboxes of the DCAN port as receiving mailbox. I set it up such that IF3 receives the incoming frame automatically, and triggers a DMA transfer (64-bit frame data) to a specified destination. I use DMA frame transfer complete interrupt to update the destination address upon each DMA frame transfer completes. So far, this works fine, but there are 32 interrupts occur in doing so.

What I am currently not able to do, but hoping to achieve is to setup DMA in a way that each IF3 NewData triggers a DMA frame transfer automatically, and once frame transfer done, the destination address gets updated automatically as well, and the next incoming CAN message frame gets automatically loaded thru IF3 and DMA to the appropriate destination. In the end, I get notified once the DMA block transfer (32 frames in my case) is done. With this, I am hoping to eliminate the number of interrupts occurring.

Is it possible to pull off a scheme as such?

Thanks,

Clio

  • 0
    TI__Mastermind 22715 points

    Clio,

    DMA cannot directly move data from DCAN mailbox to system RAM. For the reception, you always need to first move data from the specific mailbox to the IF registers before transferring to somewhere else.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Mastermind 22715 points

    Clio,

    You may want to consider the following if you want receive CAN data continuously.

    (1) Set a buffer to save data from 64 mailboxes. Assume 2x64 bit is needed for each mailbox, the total buffer size would be 128x64 bit. The DMA element size is 64 bit and each frame will have two elements. each message in a mail box will trigger a frame transfer.

    (2) Enable HBF (half buffer full) and BTC (block transfer complete) interrupts. Enable DMA auto init. In this way, you have a ping-pong buffer. When the first half of the buffer is full, the HBF interrupt occurs. CPU can process the data from the first half while DMA moves new data to the second half. When the second half is full, the BTC interrupt occurs. CPU can process the data in the second half while DMA moves data to the first half.

    (3) The DMA addressing mode should be incremental for the destination. You will need to use the index mode for source. The element index should be set such that the address will be increased by 8 after each 64 bit read. The frame index should be set such that the address will be move back to the start position in IF3 registers after the frame transfer is complete.

    Please see if the above makes sense to you.

    Thanks and regards,

    Zhaohong