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How to reset a DMA channel to its initial configured state

Chuck Wong
Genius 3950 points

Hi there,

I've posted on this thread but it seems that it was no longer followed by TI support: http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/180686/1311010.aspx#1311010

So I attempt to ask my question here.

I need at some point to reset my DMA channel to its initial state after user SW configuration for error recovery, I've read from the linked post and understood that I can write anything to this undocumented register under channel control/control packets located at address offset 0x0c, between ITCOUNT (offset 0x08) and CHCTRL (offset 0x10), to do the trick.

Can anyone confirm whether this is the right practice for such purpose?

Thanks!

  • 0
    TI__Guru**** 191486 points

    Hello Chuck,

      Sorry that your last post was probably missed out by our forum moderator of the week. To answer your question, there is no hidden register at 0xC. If you attempt to modify the control packet x when the channel x is already pending, then the DMA will automatically disable the channel x. This is documented in the TRM. Each control packet occupies 8 logical words in the memory. However, only 6 of these words store control information for the channel. The other 2 words are not used. The DMA will detect if the control packet is written when the corresponding channel is already pending by decoding a write access to any of the 8 words. Since you want to reuse the same control packet information, it is advisable to do such a dummy write to either 0xC or 0x1C using control packet 0 as an example. The data that you write to 0xC or 0x1C will never be used by the DMA but it has the effect of disabling the channel if the channel is pending.

  • 0 in reply to Charles Tsai
    Genius 3950 points

    Hi Charles,

    Therefore if I rewrite any one of the 6 DMA channel control registers with its respective existing configured value will achieve the same effect as to reset the corresponding channel. Is it?

    What do you mean by "disabling the channel if the channel is pending"? Should your statement reads "reset the channel to its initial configuration, whether it is pending or not"? Of course, if the channel is not pending, then it is already in its initial configuration.

    Thanks!

  • 0 in reply to Chuck Wong
    TI__Guru**** 191486 points

    Hi Chuck,

      Yes, if you rewrite to the control packet with the existing configured values will achieve the same effect as to reset the corresponding channel. Next time when you re-enable the channel the channel transfer will start from the beginning.

      When the channel is pending, it means that the channel has received either a hardware or a software trigger. You can check if the channel is pending in the PEND register. If the channel is already pending, meaning that a trigger is received by the DMA and you happen to write to the corresponding control packet then the DMA will disable the channel. If the channel is not pending then you can write to the control packet multiple times if you want. It is the last write to the control packet that dictates the final channel control information (source addr, dest addr, transfer count and etc) before the trigger is received.

  • 0 in reply to Charles Tsai
    Genius 3950 points

    Hi Charles,

    I must not have asked the question clearly ... I meant "the word 'disabling' only applies to the current channel pending bit, but not disabling the DMA channel from further activation". Is it?

    I assume that this will have the same RESET effect if the targeted DMA channel is currently been serviced, let say, RESET to its configured state after 10 of the 25 frames have been transferred.

    Is my understanding is still right?

    Thank you!

  • 0 in reply to Chuck Wong
    TI__Guru**** 191486 points

    Hi Chuck,

      Yes, the pending bit of the associated channel is cleared if the control packet is written to while the pending bit is active. If the channel was previously triggered by the hardware request then the HWCHENA will remain set. After the control packet is updated and a new hardware request comes, the DMA will restart with the orignal control information. Using your example, if you write to the control packet after 10 out of 25 frames are transferred then the pending bit is cleared and a new hardware request will restart the transfer from frame 1, not frame 11 or any element where it left out. The DMA has no way of knowing what you modify to the control packet, whether you change to a new source/dest address or different number of transfe counts and etc. The key is that the DMA will restart from the very beginning based on your new channel packet information. If the channel was previously triggered by a software request then the associated pending bit in the PEND register and the associated bit in the SWCHENA register will be cleared. The CPU needs to write to the SWCHENA for the channel to restart from the new control packet information.

  • 0 in reply to Charles Tsai
    Genius 3950 points

    Very clear! Thank you Charles.

    I've also posted a DMA related question when working with the MCU-integrated I2C module yesterday, no reply yet as of today. Would it be possible for you to take a peek on it?

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/373549.aspx

    In any case, your support is greatly appreciated.

    Regards.