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TM4C123GH6PM datasheet - Bug in DMA info?

Other Parts Discussed in Thread: TM4C1294NCPDT

Hi everyone,

I found some conflicting information on the datasheet.

In table 9-1 it says that all GPIO only have burst request ability. In table 9-2 it says the opposite, which one is it?

Also, i take this advantage to ask one more thing, does the GPIO support DMA done interrupt?  

  • Hello Luis

    Thanks for bringing it up. I will check and confirm but indeed it is two conflicting statements,

    The DMA Done Interrupt is indicated on the Peripheral Interrupt Vector.

    Regards

    Amit

  • Hi Amit,

    Could you please guide me where can i find that in the datasheet? I'm having a bit of trouble finding the information, i usually find interrupt info in the registers and the functional description 

    Also, unlike the Tm4C1294NCPDT, there isn't any reference to a DMA done interrupt in the GPIO part

  • Hello Luis,

    TM4C123 had a different architecture for DMA Done for all peripherals as compared to TM4C129.

    For the GPIO it is not mentioned as to how the whole mechanism works. The user has to enable the Interrupt for the GPIO in the NVIC and set up the GPIODMACTL. On completion the GPIO Interrupt will be asserted. The user application code then has to go and check if the DMA Status for the GPIO Channel shows a STOP condition or not. If it does then the interrupt is from the DMA Channel completion

    Regards

    Amit

  • Hi Amit,

    Yes i understand that, i only wanted to note that the TM4C129 clearly states the interrupt is possible (at least more clearly for me).

    I use TivaWare most of the times and so usually dealing with the NVIC is not necessary. I have a similar code in the TM4C129 that i ported to the TM4C123. The interrupt never happens. 

    Maybe in the TM4C123 i need to something else. I use this: 

      MAP_GPIOIntTypeSet(    GPIO_DMA_BASE1,GPIO_DMA_PIN1,GPIO_BOTH_EDGES);
      GPIOIntRegister( GPIO_DMA_BASE1,GPIOPort1IntHandler);
    
      MAP_GPIOIntClear( GPIO_DMA_BASE1,0x1FF);
    
      MAP_GPIODMATriggerEnable( GPIO_DMA_BASE1,GPIO_DMA_PIN1);
    
      MAP_GPIOIntEnable( GPIO_DMA_BASE1,GPIO_INT_DMA);
    
      MAP_IntEnable(INT_DMATRIGGER1);

    Sincerely i rarely even use IntEnable(); and it always works, for any type of interrupt. Could you give me some advises. Maybe i am doing something that as been working so far but it's incorrect

    EDIT:

    If the GPIO only accepts single requests this could be the problem

  • Hello Luis,

    There is no Interrupt Mask bit for DMA in TM4C123 in the peripheral address space. Hence the GPIOIntEnable will not have an effect.

    Secondly, the use of GPIOIntRegister API will enable the interrupt in the NVIC as it calls IntEnable API.

    Is the DMA Initialized for the GPIO, you may want to attach the full code so that I can review the same.

    Regards

    Amit

  • Hi Amit,

    Ah finally found that in the tm4c1294 there is a specific bit for the DMA done. Thanks.

    That's the problem itself. The code will simply not work without it.

    There isn't a interrupt DMA done, well suddenly i like the tm4c1294 more. 

    When you get the info, can you confirm what requests does the GPIO generate for the DMA, Burst or Single? 

  • Hello Luis,

    Yes, from a DMA implementation perspective even I like the TM4C129 series more. I checked and it is a Single Request. However the uDMA can be configured to transmit a burst of data using the ARBSIZE field in the control word for the channel.

    Regards

    Amit

  • Hi Amit,

    Ahh, i've been around so much other peripherals that i forgot. What i actually need is a single request. In Arb Size i would always use size 1 for my application, in the tm4c1294.

    But still, if the GPIO only triggers a single request, the ARBSIZE won't do anything right, in the tm4c123

  • Hello Luis,

    By setting Burst Only mode and configuring ARB Size, you can do more than one transfer when a single request is asserted. The concept of Single and Burst Request makes more sense for Data Transfer peripherals which generate the signals based on the FIFO conditions.

    Regards

    Amit