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DMA Channel Chaining in TMS570LS3137

Archana Kumarraj60
Prodigy 215 points
Other Parts Discussed in Thread: TMS570LS3137

Hi,

I am using SPI4 and DMA of TMS570LS3137

I am tx data from three distinct buffer to SPIDAT1 register  of SPI 4(compatibility mode) using DMA.

I need to transmit data from buffers to SPIDAT1 in this order-

1st data of buffer1 to SPIDAT1, 1st data of buffer2 to SPIDAT1, 1st data of buffer3 to SPIDAT1                               2nd data of buffer1 to SPIDAT1  , 2nd data of buffer2 to SPIDAT1, 3nd data of buffer3 to SPIDAT1

and so on.....

To achieve this I am using channel chaining option of DMA,

But the problem is Channel is not chaining properly.

For ex:

Buffer1={1,2,3,4,5,6,7,8, 9, 10}

Buffer2= {11,12,13,14,15,16,17,18,19,20}

Expected transmission sequence= 1,11,2,12,3,13,4,14,5,15,6,16,7,17,8,18,9,19,10,20 

But I am getting something like this- 1,20,10,19,18,8,17,7,6,15,5,14,13,3,12,2,1 and repeat   

Chain is missing as above and as the number of buffer elements increases the buffer elements are getting transmitted to SPIDAT1 more randomly.                                                                                                                                                                              

 I have set following things

       SPI to 0.8Mhz

  • assigned  channles to high priority queue 
  • seleted channel Rotation scheme
  • Parity is disabled
  • FIFO is not bypassed.
  • write and read data size is 32 bits( control word+data)
  • frame count = 10, element count =1
  • source frame index is 4, element index = 0
  • dest frame index is 0, element index = 0
  • auto init is enabled.
  • channel 3 is chained to channel 2
  • channel 2 is chained to channel 3.
  • selected frame transfer type.
  • read addressing mode is post-indexed, write addressing mode is constant.

 

 

 

 

 

  • 0
    TI__Guru**** 197446 points

    Hello,

    Please refer to the following thread about how to use DMA channel chain. A CCS project example is embedded in this thread.

    https://e2e.ti.com/support/microcontrollers/hercules/int-hercules/f/365/p/352471/1235722.aspx#1235722

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Prodigy 215 points

    This group is not found. Can you pls resend the link

  • 0 in reply to Archana Kumarraj60
    Prodigy 215 points

    Pls. send me link of code examples, where SPI is used in compatibility mode and DMA channel chaining is used.

  • 0 in reply to QJ Wang
    Prodigy 30 points

    Hi, The above link doesnt not lead to any code modules. We are hard pressed on time and wanted example for SPI - DMA chaining example.

  • 0 in reply to Shailashri Kuruvatti84
    TI__Guru**** 191906 points

    Hello Shailashri,

      The issue is not the DMA chaining setup. I think the problem is that the SPI only supports double buffering and not more. In the SPI, there is a TXBUF and the shift register. When both of them are empty, a write to either SPIDAT0 or SPIDAT1 register will copy the data to the shift register. If the shift register is not empty then the next write to either SPIDAT0/SPIDAT1 will copy the data to the TXBUF. After the data is shifted out from the shift register the data in the TXBUF is then copied to the shift register and at this time a transmit DMA request is generated. When this DMA request is generated, the DMA will transfer the first element of both the channels. In your example, this means that data 0x1 and 0x11 are transferred to the SPIDAT0/SPIDAT1 register. However, the data in the current shift register is not yet completely shifted out yet. You are transfering two elements to the SPIDAT0/SPIDAT1 when the TXBUF can only hold one data. DMA first transfers 0x1 to the SPIDAT0/SPIDAT1 register but immediately the data (0x1) in the register is overwritten with 0x11. 

  • 0 in reply to Charles Tsai
    Prodigy 215 points

    Hi,

    Can anyone pls. help me out.

    I need to transmit buffer data to SPIDAT1 register as below-

    Buffer1={e1,e2.....en} Buffer2={f1,f2.....fk}

    DMA channel 1 should transfer e1 and control should be passed to channel 2 to transmit f1. channel 1 should transfer e2 and control should be passed to channel 2 to transmit f2.

    like this after n elements of buffer1 and k elements of buffer2 are transmitted, the above sequence should repeat.

    channel should switch for every single transfer.

     Channel Priority schemes doesnt yield this.

    Need to achieve this without CPU intervention.

    Quick responses are appreciated.

    Regards,

    Archana

  • 0 in reply to Archana Kumarraj60
    TI__Guru**** 191906 points

    Hi Archana,

      As mentioned in the previous reply the DMA chaining can not achieve what you want as two writes from the DMA will ovewrite the TXBUF.

      What you can do is to setup two independent channels, not chained to each other. The DMA request from the SPI will trigger each channel alternatively. You first map the SPI3 TX DMA request to the first channel. You will need to enable the FTC (frame transfer complete) interrupt of each DMA channel too. The first time a DMA request is received the first channel will write e1 to SPIDAT1 and an interrupt is generated for the first channel. In the interrupt service routine you will disable the mapping of SPI3 TX DMA request to the first channel and instead map DMA request to the second channel. Next time when a DMA request is generated it will trigger the second channel to transfer f1 and generate an interrupt again. This time in the ISR you will reverse the DMA request to the channel mapping by mapping the DMA request to the first channel again. This is an idea. CPU will need to intervene to service the interrupt.

     Can you not merge both buffers in an interleave fashion before transfering?