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NMI Trigger Level (TM4C1294NCPDT)

Soumyajit Das
Genius 3340 points
Other Parts Discussed in Thread: TM4C1294NCPDT, EK-TM4C1294XL

Hi,

   I have been assigned a project where I have to design (schematic & firmware) an application with TM4C1294NCPDT where I need to use NMI interrupt (pin no. 128 on the chip). I have gone through the NMI section of the Datasheet of this chip but I am unable to understand whether NMI interrupt is level triggered or edge triggered and also whether the level can be configured to logic high or logic low or is it fixed. If someone can tell where to look for (which section/page no.) in the datasheet, that will help too.

   Also would like to know which registers to set in order to set NMI trigger levels.

   For testing purposes, I have been provided with a purchased EK-TM4C1294XL and I intend to test the NMI functionality on this eval kit.

Thanks

  • 0
    Guru 26105 points

    Hi,

    On page 228 you can read this:

    5.2.3.1  NMI Pin

    The NMI signal is an alternate function for the GPIO port pin(s) specified in Table 26-3 on page 1785.

    The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 742. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function, similar to the requirements of the GPIO port pins associated with JTAG/SWD functionality, see page 784. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH initiates the NMI interrupt sequence.

    Further info is in GPIO chapter. Note in paragraph above: the signal is level active, High.

    Petrei

     

  • 0 in reply to Petrei
    Genius 3340 points

    Thanks a lot Petrei....