Hi,
we are using the TMS570LS3137 in our application. To prevent speculative prefetch ECC errors we are programming the ECC values for the entire bank0 and bank1 normal flash area.
In the TRM there is written that the Cortex R4 CPU is not generating any speculative prefetches into the bank7 address space (flash emulated EEPROM).
How are the OTP regions treated? Are there also no speculative prefetches possible in the entire flash bus2 interface?
