TMS570LS3137 MPU code in HALCoGen

Charles Johnston

Other Parts Discussed in Thread: HALCOGEN

Hello,

The MPU code generated by HALCoGen includes a Data Synchronization Barrier (dsb) instruction after the reading of the SCTLR and an Instruction Synchronization Barrier (isb) instruction after the writing of the SCTLR. I have to provide a justification for all code, so I was wondering why these sync instructions were used here. Are they needed for access to SCTLR, or are they needed because the MPU is disabled/enabled?

Thanks, Charlie Johnston

over 10 years ago

0 Jean-Marc Mifsud over 10 years ago

TI__Mastermind 22375 points

Charlie,

The DSB instruction is necessary to insure that all data access are performed prior to change the state of the MPU.

Here is an extract from ARM Cortex R4 TRM.

Basically the DSB instruction insures that all data accesses are done before changing the MPU state (Enable/Disable)
The ISB intruction insures that no other instruction will be executed until the MPU state is changed.

Please let me know if this answers your question.

0 Charles Johnston over 10 years ago in reply to Jean-Marc Mifsud

Expert 2690 points

Jean-Marc,

That's exactly what I was looking for. I didn't search down far enough.

Thank you very much.

Charlie Johnston

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LS3137 MPU code in HALCoGen