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Linker Changes for RM48 Sample Bootloader

Matt Harding
Prodigy 220 points
Other Parts Discussed in Thread: HALCOGEN, TMS570LS3137, RM48L950

Hello,

I'm attempting to use the sample CAN Bootloader (from http://processors.wiki.ti.com/index.php/RM4x_Hercules_MCU_Bootloader) project for RM48 using CCS6 and HALCOGEN4.0.0

I got the bootloader to compile fine, now I'm looking for what I need to change in my application for it to work with the bootloader. Are there changes to the linker file that I need to make?

Thanks,

Matt

  • 0
    TI__Guru**** 197036 points

    Hi Matt,

    The user guide on the WIKI page is out of date. Please use the link below to find the user guide for RM48x CAN bootloader. The section #10 is the example how to modify the cmd file for the application project. 

    http://www.ti.com/lit/an/spna184/spna184.pdf

    I will update the WIKI shortly. Thanks

    Regards,

    QJ

  • 0
    TI__Mastermind 22375 points

    Matt,

    This bootloader expects the application code to start at address 0x0002_0000 for the vector table and 0x00020020 for the application itself.

    Here is the linker command file I'm using for the BLINKY test case when used with the bootloader.

    /*----------------------------------------------------------------------------*/
    /* sys_link.cmd */
    /* */
    /* (c) Texas Instruments 2009-2013, All rights reserved. */
    /* */
    /*----------------------------------------------------------------------------*/
    /* USER CODE BEGIN (0) */
    /* USER CODE END */


    /*----------------------------------------------------------------------------*/
    /* Linker Settings */

    --retain="*(.intvecs)"

    /* USER CODE BEGIN (1) */
    /* USER CODE END */

    /*----------------------------------------------------------------------------*/
    /* Memory Map */

    MEMORY
    {
    VECTORS (X) : origin=0x00020000 length=0x00000020
    FLASH0 (RX) : origin=0x00020020 length=0x0013FFE0
    STACKS (RW) : origin=0x08000000 length=0x00001500
    RAM (RW)    : origin=0x08001500 length=0x0002EB00

    /* USER CODE BEGIN (2) */
    /* USER CODE END */
    }

    /* USER CODE BEGIN (3) */
    /* USER CODE END */


    /*----------------------------------------------------------------------------*/
    /* Section Configuration */

    SECTIONS
    {
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0
    .const   : {} > FLASH0
    .cinit   : {} > FLASH0
    .pinit   : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

    /* USER CODE BEGIN (4) */
    /* USER CODE END */
    }

    /* USER CODE BEGIN (5) */

     

    Please let me know if this is helpfull.

  • 0 in reply to Jean-Marc Mifsud
    Prodigy 220 points

    Thank you both very much. I have modified the linker file and the application seems to function as expected. The default linker file I was using (generated by HALCOGEN) contains not only FLASH0, but also FLASH1. I have not found a description of what these two flash definitions are or what they mean. Could either of you shine some light on that?

    Thanks,

    Matt

  • 0 in reply to Matt Harding
    TI__Mastermind 22375 points

    Matt,

    Depending on the device you are using, you may have 1 or 2 flash bank.

    For example, the TMS570LS3137 has a total of 3MB of Flash.
    Bank0 is 1.5MB and Bank1 is 1.5MB

    In the linker, you have 2 memory section named:

    FLASH0 that covers the bank0
    FLASH1 that covers the bank1.

    In my example the device I was using only has 1 bank (Bank0) named as FLASH0 in the linker command file.

    Please let me know if this is clear.

  • 0 in reply to Jean-Marc Mifsud
    Prodigy 220 points

    Thanks Jean-Marc, that is clear. I now see in the datasheet for RM48L950 in section 4.10, it describes flash bank 0 containing 15 sectors and flash bank 1 contains 12 sectors. I still do not understand why there are 2 separate banks of 1.5M each instead of a single bank of 3MB. But I suppose that is superfluous.

  • 0 in reply to Matt Harding
    TI__Mastermind 22375 points

    Matt,

    The main reason is access time and performance.

    An indirect value of having more than 1 bank of flash is the capability to execute code / access data from one bank and being able to erase/program the other one.

    On a single bank device, to be able to program/erase the flash, the execution has to be done from RAM.
    That means, the flash algorithm has to be copied from Flash to RAM first and than executed from RAM.

  • 0 in reply to Jean-Marc Mifsud
    Prodigy 220 points

    Thank you for the information. That certainly helps my understanding.