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TMS570LS3137 PCR initialization

Charles Johnston
Expert 2690 points
Other Parts Discussed in Thread: TMS570LS3137, HALCOGEN

Hello,

SPMU499B shows the PCR registers PCSPWRDWNSET0, PCSPWRDWNSET1, PCSPWRDWNCLR0, and PCSPWRDWNCLR1 as inactive (1) after reset, but show up as active (0) after reset on the HDK.  Is this a typo, or is there something else setting the peripheral memory clocks active after reset?

Thanks, Charlie Johnston

  • 0
    TI__Mastermind 22375 points

    Charlie,

    On SPNU99B, in the description for Peripheral Memory Power-Down Set/Clear Register 0/1 there is a note saying:

    Only the bit that have a slave at the corresponding position are implemented. Writes to nonimplemented bits have no effect and reads are 0.

    This is what you are seeing.

    On TMS570LS3137, the peripheral memory power-down is controlled via the Peripheral Power-Down Set/Clear Register 0/1

    For example, the N2HET RAM is automatically power down when N2HET is power down.
    It is not possible to power down N2HET Ram only and keep N2HET on.

    The same applies for MIBSPIs and MIBADCs.

    Please let me know if I've answered your question.

     

  • 0 in reply to Jean-Marc Mifsud
    Expert 2690 points

    Hi Jean-Marc,

    I must be interpreting the TRM incorrectly.  Please check my logic.

    This is the status of the PCR Power Down registers after reset:

    This shows all Peripheral Memory Clocks are active (0) or not implemented.  The TRM says that implemented Peripheral Memory Clocks are set inactive (1) after reset.  The values of the PCSPwrDwn registers can't be modified while halted in debug mode. 

    1) Could the debugger be displaying the registers incorrectly, or are these registers affected by halting the debugger?

    2) If the Peripheral Memory Clocks are inactive after reset, how are they activated?  There is no write to the PCSPwrDwnClr registers the HALCoGen initialization path, explicit writes would have to be added by the application code.

    Thanks, Charlie Johnston

  • 0 in reply to Charles Johnston
    Expert 2690 points

    Hi Jean-Marc,

    The image did not get into the post - let's try again:

    Thanks, Charlie

  • 0 in reply to Charles Johnston
    TI__Mastermind 22375 points

    Charlie,

    Your logic is correct, but in all Hercules parts, the PCSPwrDwn are not usedat all. Instead, the clock control for the peripheral memory is done via the PSPwrDwn.
    In other words, as soon as a peripheral module is clocked, is corresponding memory (if available) is also clocked.
    This is true for N2HET, MIBSPI, MIBADC.

    Mainly the rational behind this implementation is, the peripheral module cannot be used if it's corresponding memory is not clocked. So once the peripheral is out of power down, it's memory is also out of power down.

    /** - Disable Peripherals before peripheral powerup*/
    systemREG1->CLKCNTL &= 0xFFFFFEFFU;

    /** - Release peripherals from reset and enable clocks to all peripherals */
    /** - Power-up all peripherals */
    pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
    pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
    pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
    pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;

    /** - Enable Peripherals */
    systemREG1->CLKCNTL |= 0x00000100U;

    Please let me know if this is clear.

  • 0 in reply to Jean-Marc Mifsud
    Expert 2690 points

    Hi Jean -Marc,

    It makes sense now.  You may want to have the TRM folks add this to the next revision.

    Thanks, Charlie Johnston

  • 0 in reply to Charles Johnston
    TI__Mastermind 22375 points

    Charlie,

    This should be a clarification part of the datasheet not the TRM.

    I will highlight this point to the documentation team.

    Thanks,