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Only 2 first frames transferred by DMA with MIBSPI5

Brice Plavonil
Intellectual 720 points
Other Parts Discussed in Thread: HALCOGEN

Hello,

Configuration:

RM48X Safety Hercules Microcontroler,

Halcogen 03.06

My problem:

I use the MIBSPI5 in slave mode 3 wires (CLOCK,CS, SIMO) with DMA

the MIBSPI5 receive data of 32-bits long that I managed to check in the memory  0xFF0A0200

I tuned the DMA for transferring 11 frames of dsize 2 (2 x 16-bits).

I set in the MIBSPI DMA config:

bufid = dsize-1
 and icount = numbOfframe-1

I send exactly 11 x 32-bits of data in the MIBSPI ( the CS is set  low  then high for each 32-bit...)

Result: the data appears in the MIBSPI5 memory but are partly  transferred into the RAM by the DMA.

--> Only the 2 first frame are transferred

in the MIBSPI5 register UErrCtrl I have 0x0000000A

and UErrAddr1 0x00000248

and the 2 first memory address of the data in MIBSPI5 start with 8 meaning that : No data has been received since the last read of SPIBUF. (which I think is correct)

the other buffers address starts with 0  :New data has been received and copied into the SPIBUF field.

here is a snapshot of the MIBSPI memory and the buffer where DMA transfers the values

When I simply change the numbe of frame to 1 and the size to 22 the buffer is filled with the values from the MIBSPI memory

however I still have the error bit set in the register

UErrCtrl I have 0x0000000A
and UErrAddr1 0x00000248

I really want to know why it does not work with the first configuration

Could Someone gives me a clue on this ?

here after the snapshot after modification

  • 0
    TI__Mastermind 22375 points

    Brice,

    According to your post, the MIBSPI receives all the data correctly.
    MIBSPI will, on completion of the transfer group, generate 1 DMA request.

    On the DMA side, you I think you have configure as frame transfer triggered.
    This explains why you are only seeing the first 2 elements being transferred.
    When you change your code to 1 frame of 22 elements, than it is working.

    See this picture:

    You can change the configuration from Frame triggered to Block trigger with 11 frames of 2 elements and get the same result.

    Concerning the UErrAddr1, the value is only relevant if UERRSTAT bit 0 or 1 is set. If these bits are 0s that means there is no problem.

    Please let me know if this answers your question.

     

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 720 points

    Hello Jean-Marc,

    According to this picture it is possible to get  a DMA request generated each time a frame is full. The picture 1 is exactly what I intended to have.

    I made the same test for another configuration (still in frame mode):

    the MIBSPI receives  64-bits long data with the same process (Clock, CS, Data). I checked the data and it is all right.

    When I use DMA  this time by configuring  the number of element to  4 (4 x16-bits), I can generate in a buffer whatever number of frame I want.

    it works for number of element = 4

    quite bizarre

    I can send you the snap shot for the 64-bits I you want to. 

    Could this problem rely on the bufid and icount of the DMACTRL register  in the MIBSPI ?

    Brice

  • 0 in reply to Brice Plavonil
    TI__Mastermind 22375 points

    Brice,

    The picture 1 (from DMA User Guide) is what the DMA expects in Frame mode, not what the mibspi is doing.

    I will need to see your full MIBSPI and DMA configuration to better understand what is going on.

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 720 points

    Hello Jean-Marc,

    I just shared privately under  the "Conversation" profil the MIBSPI configuration and the main.

    thank you for your help.

    please tell me if you need anything else.

    Brice

  • 0 in reply to Brice Plavonil
    TI__Mastermind 22375 points

    Brice,

    Here is the reply from MIBSPI designer:

    Your understanding is correct.

    In this specific case, you must set the TG0 to support just 4 buffers. If Buf3 (4th buffer) is set as the DMA buffer (BUFFID), then MIBSPI will trigger a DMA request when this buffer is copied with RX data. DMA controller is expected to read out all of the RX buffers as a response.

    If you’ve configured TG0 to repeat (ONESHOT=0), then it will keep repeating this. MIBSPI will request ICOUNT number of DMA requests and then stop the requests.

    Please let me know if this fully answers your question.