TM4C1290NCPDT SSI not working

Other Parts Discussed in Thread: TM4C1290NCPDT

I am using AT45DB041E Dataflash with TM4C1290NCPDT.

I am using SSI0 for interfacing the IC.

CS pin of IC is permanently tied to ground. SSI0XDATA0 is connected to SI and SSI0XDATA1 is connected to SO & SSI0Clk is connected to SCK pin of IC. PA0 is used as GPIO and connected to RESET pin of IC. All pin is externally Pull-up.

Below is my SSI0 configuration code and SSI transmit code.

void SSI_0_Configuration(void)
{
    //
    // The SSI0 peripheral must be enabled for use.
    //
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);

    //
    // For this example SSI0 is used with PortA[5:2].
    //
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

    //
    // Configure the pin muxing for SSI0 functions on port A2, A3, A4, and A5.
    //
    ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
    //ROM_GPIOPinConfigure(GPIO_PA3_SSI0FSS);
    ROM_GPIOPinConfigure(GPIO_PA4_SSI0XDAT0);
    ROM_GPIOPinConfigure(GPIO_PA5_SSI0XDAT1);

    //
    // Configure the GPIO settings for the SSI pins.  This function also gives
    // control of these pins to the SSI hardware.  Consult the data sheet to
    // see which functions are allocated per pin.
    // The pins are assigned as follows:
    //      PA5 - SSI0Tx
    //      PA4 - SSI0Rx
    //      PA3 - SSI0Fss
    //      PA2 - SSI0CLK
    //
    ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);

    //ROM_SSIAdvModeSet(SSI0_BASE, SSI_ADV_MODE_LEGACY);

    //
    // Configure and enable the SSI port for SPI master mode.  Use SSI0,
    // system clock supply, idle clock level low and active low clock in
    // freescale SPI mode, master mode, 50MHz SSI frequency, and 8-bit data.
    // For SPI mode, you can set the polarity of the SSI clock when the SSI
    // unit is idle.  You can also configure what clock edge you want to
    // capture data on.  Please reference the datasheet for more information on
    // the different SPI modes.
    //
    ROM_SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
                       	   SSI_MODE_MASTER, 1000000, 8);

    //
    // Enable the SSI0 module.
    //
    ROM_SSIEnable(SSI0_BASE);

    //
    // Read any residual data from the SSI port.  This makes sure the receive
    // FIFOs are empty, so we don't read any unwanted junk.  This is done here
    // because the SPI SSI mode is full-duplex, which allows you to send and
    // receive at the same time.  The SSIDataGetNonBlocking function returns
    // "true" when data was returned, and "false" when no data was returned.
    // The "non-blocking" function checks if there is any data in the receive
    // FIFO and does not "hang" if there isn't.
    //
    while(ROM_SSIDataGetNonBlocking(SSI0_BASE, (uint32_t *)&DataFlash_RxBuffer[0]));

	ROM_GPIOPinTypeGPIOOutput(DATAFLASH_RESET_CS_PORT, DATAFLASH_RESET_PIN);

	ROM_GPIOPinWrite(DATAFLASH_RESET_CS_PORT, DATAFLASH_RESET_PIN, DATAFLASH_RESET_HIGH);
}

void DataFlash_Transmit(unsigned int Length)
{
	unsigned int i;

	for(i=0; i < Length ; i++)
	{
		ROM_SSIDataPut(SSI0_BASE, DataFlash_TxBuffer[i]);

		while(ROM_SSIBusy(SSI0_BASE));

		ROM_SSIDataGet(SSI0_BASE, &DataFlash_RxBuffer[i]);
	}
}

The problem is that get 0xFF data in receive buffer. So i think that communication isn't established. So is it hardware or software issue?