I have a customer who wants to connect the DAC8728 to the EMIF interface of the RM46L430. We have reviewed both Datasheets and see no reason why this would not work properly. Can you confirm our findings. Thank you
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Michael,
The EMIF on RM46x drives the chip-select signal (nCS) low along with the RnW, address and data (for writes). This is followed by the SETUP time, after which the read-enable or write-enable signals are asserted.
This does not meet the min 2ns delay requirement between RnW falling to nCS falling. Also, the DAC requires a min 6ns from a valid address to nCS falling. This is not met either.
Regards,
Sunil
Hi Sunil,
Is there any workaround? Can I add a delay in nCS line?
How to connect parallel DAC to RM46L430?
As I know, there are only 16GPIO pins available on 337pin package.
I might be wrong, please comment.
Thanks,
Goran
Sunil,
Can we use the programmable asynchronous features of the EMIF to meet the DAC timing?
4.14 External Memory Interface (EMIF)
4.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
• 3 addressable chip select for asynchronous memories of up to 16MB each
• 1 addressable chip select space for SDRAMs up to 128MB
• 8 or 16-bit data bus width
• Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
• Select strobe mode
• Extended Wait mode
• Data bus parking
Michael,
The programmable timings configure the SETUP, STROBE and HOLD times for the asynchronous interface. However, these do not help you change the order in which the control signals are asserted. This particular DAC requires all other control signals and address/data (for writes) to be asserted some time before the chip select is asserted. This cannot be managed using the timing configuration registers available in the EMIF.
You can certainly use means to delay the chip-select signal externally to make the interface work, however.
Regards,
Sunil