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RM46L430 EMIF to DAC8728 Interface

Michael Stibila
Prodigy 205 points
Other Parts Discussed in Thread: DAC8728, RM46L430

I have a customer who wants to connect the DAC8728 to the EMIF interface of the RM46L430. We have reviewed both Datasheets and see no reason why this would not work properly. Can you confirm our findings. Thank you

  • 0
    TI__Guru 59540 points

    Hello Michael,

    I have forwarded your question/request to one of our EMIF experts. They will get back with you soon.

  • 0
    TI__Mastermind 49120 points

    Michael,

    The EMIF on RM46x drives the chip-select signal (nCS) low along with the RnW, address and data (for writes). This is followed by the SETUP time, after which the read-enable or write-enable signals are asserted.

    This does not meet the min 2ns delay requirement between RnW falling to nCS falling. Also, the DAC requires a min 6ns from a valid address to nCS falling. This is not met either.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 10 points

    Hi Sunil,

    Is there any workaround? Can I add a delay in nCS line?

    How to connect parallel DAC to RM46L430?

    As I know, there are only 16GPIO pins available on 337pin package.

    I might be wrong, please comment.

    Thanks,

    Goran

  • 0 in reply to goran igic
    Prodigy 205 points

    Sunil,

    Can we use the programmable  asynchronous features of the EMIF to meet the DAC timing?

    4.14 External Memory Interface (EMIF)

    4.14.1 Features

    The EMIF includes many features to enhance the ease and flexibility of connecting to external

    asynchronous memories or SDRAM devices. The EMIF features includes support for:

    • 3 addressable chip select for asynchronous memories of up to 16MB each

    • 1 addressable chip select space for SDRAMs up to 128MB

    • 8 or 16-bit data bus width

    • Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time

    • Select strobe mode

    • Extended Wait mode

    • Data bus parking

  • 0 in reply to Michael Stibila
    TI__Mastermind 49120 points

    Michael,

    The programmable timings configure the SETUP, STROBE and HOLD times for the asynchronous interface. However, these do not help you change the order in which the control signals are asserted. This particular DAC requires all other control signals and address/data (for writes) to be asserted some time before the chip select is asserted. This cannot be managed using the timing configuration registers available in the EMIF.

    You can certainly use means to delay the chip-select signal externally to make the interface work, however.

    Regards,

    Sunil