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Initialize ADC on tm4c123g for sequence 0 operation with oversampling



Hi guys

I'm having some trouble properly configuring the ADC on my TM4C123G board for sequence 0 with oversampling. I've read through many examples in these forums and the datasheet but I'm unsure what is causing my error. Here is my code to initialize the ADC:

//ADC Definitions
#define ADC_SEQ_NUMBER			0
#define ADC_PRIORITY_LEVEL		0
#define ADC0_OVERSAMPLE_RATE	        64//Must be exponent of two, no more then 64
#define NUM_OF_ADC_PINS			8
#define PORT_B_ADC_PINS			(GPIO_PIN_5)
#define PORT_D_ADC_PINS			(GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3)
#define PORT_E_ADC_PINS			(GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_5)

//-----------------------------------------------------------------------------------------

void initADC()
{
	//Enable the ADC
	SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
	SysCtlDelay(3);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
	SysCtlDelay(3);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
	SysCtlDelay(3);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
	SysCtlDelay(3);

	//Set ADC PINS
	GPIOPinTypeADC(GPIO_PORTB_BASE, PORT_B_ADC_PINS);
	SysCtlDelay(3);
	GPIOPinTypeADC(GPIO_PORTD_BASE, PORT_D_ADC_PINS);
	SysCtlDelay(3);
	GPIOPinTypeADC(GPIO_PORTE_BASE, PORT_E_ADC_PINS);
	SysCtlDelay(3);

	//Set ADC to sample at 500 KSPS and then average 64 of them for each result
	SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
	SysCtlDelay(3);
	ADCHardwareOversampleConfigure(ADC0_BASE, ADC0_OVERSAMPLE_RATE);//ENTER FAULTISR HERE!!!
	SysCtlDelay(3);

	//Turn off ADC sequence before configuring
	ADCSequenceDisable(ADC0_BASE, ADC_SEQ_NUMBER);//If I remove the oversampling, it enters the FAULTISR HERE
	SysCtlDelay(3);

	//Configure the ADC - Sequence 0 -> 8 steps
	ADCSequenceConfigure(ADC0_BASE, ADC_SEQ_NUMBER,
						 ADC_TRIGGER_PROCESSOR, ADC_PRIORITY_LEVEL);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 0, ADC_CTL_CH1);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 1, ADC_CTL_CH2);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 2, ADC_CTL_CH4);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 3, ADC_CTL_CH5);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 4, ADC_CTL_CH6);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 5, ADC_CTL_CH7);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 6, ADC_CTL_CH8);
	ADCSequenceStepConfigure(ADC0_BASE, ADC_SEQ_NUMBER, 7, ADC_CTL_CH11 | ADC_CTL_IE |
							 ADC_CTL_END);

	//Enable the sequence and clear the interrupt flag
	ADCSequenceEnable(ADC0_BASE, ADC_SEQ_NUMBER);
	ADCIntClear(ADC0_BASE, ADC_SEQ_NUMBER);
}

The code builds and starts to run, but I've marked which lines put me into the faultISR. The goal of this program is to use the 8 analog input pins on the evaluation board to sample some sensors.

Another question that I have, is that if there is 12 analog in pins, why can each sequence only have a FIFO depth of (up to) 8? To utilize all pins, does one have to use both ADC converters?

Eventually, I would like to use the comparators but would like to get this code working first.

  • Hi Austin,

         See, this post below.

         SysCtlADCSpeedSet()

    - kel

  • Hello Austin

    What is the System Clock Source being used? Please note that there is an Errata for Clock Source for System v/s ADC on TM4C123. I am asking the question as it was not very clear here in the code as to the source of system clock

    As for the second part of the question. There are 24 ADC channels and not 12. The ADC Channels can be mapped between the two ADC's. Also in each ADC there are 4 sequencers with combined sequence steps of 17 (8+4+4+1). Hence out of 24 channels any 17 can be mapped. If all channels are required then both ADC's are required (unless dynamic changes are being sought after).

    Regards

    Amit

  • Thanks for the answers, Amit and Kel. I was using the PLL as the source Amit. Kel, after reviewing your post I noticed that I had out of date TivaWare. I updated my TivaWare (in addition to jumping to ccs 6) and this seems to have fixed my issue.