Question regarding the TMS570LS4357 CPU interconnect self test

Libo Luo

Hello forum team,

I have a few questions regarding the TMS570LS4357 CPU interconnect self test.

According to TRM Section 3.3.2 (Step 1) SDC_COTROL.MASK_SOFT_RESET (0xFA000004[0]) shall be set to 0. Because of the erratum DEVICE#51, the byte3 and byte0 are swapped. In debugger I can see that both write and read access shall swap the two bytes. If I write 0x0000000F to this address, then the value is still 0x00000000. If I write 0xFF000000, then the value is changed to 0x1F000000.

Q1: According to TRM, only bit 0 at this address is defined. Do the other bits [4:1] have any meaning?

Q2: It makes no difference which bit in 0xFA000004[0] shall be written if I write 0x00000000 to this address. But I would like to confirm that I should write DATA with DATA[28] equal 0 to this address to enable the CPU interconnect self test.

Q3: After the test (CPU reset triggered by the self test), I checked the register SDC_STATUS, it is 0x00000000. According to TRM, I expect that SDC_STATUS.NT_OK and SDC_STATUS.PT_OK both to be 1. Maybe here there are typos in TRM? Both bits shall be 0 if tests passes?

Thank you and best regards,

Libo

over 10 years ago

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago

TI__Genius 11645 points

Libo,

I'll take a look at this and get back to you soon.

0 Libo Luo over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Intellectual 940 points

Hi Karthikeyan,

any update here? Esp. to Question 3? Did you reproduce the effect I described above?

Thanks and regards,

Libo

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to Libo Luo

TI__Genius 11645 points

Hi Libo,

Sorry for the delay, one of our engineers will respond to this by today/tomm.

0 Praveen Kumar Ravichandran over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

TI__Expert 4610 points

Hello Libo,

We are able to reproduce the issue at our end. We shall consult with our design team on this and get back to you.

Thanks,
Praveen

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to Praveen Kumar Ravichandran

TI__Genius 11645 points

Hello Libo,

Apologies for the delay, it took a while for us to dig in to the design understanding the issue.

Especially on #3 we see those registers getting set but unfortunately before the CPU experiences a reset and goes back to check they get cleared by the hardware.

For now what we would suggest you is to check the source of reset and if the same results to be due to interconnect self test, then go ahead and read the ESM status register to make sure CPU Interconnect Subsystem - Diagnostic Error is not set, which should guarantee that no error had occurred during the self-test(Group-3 Channel-12).

Regarding #1 those registers are not documented in the specs but please keep them ([4:1]) set to zero(They should not affect the Interconnect self-test). We will update the documentation at the earliest possible with relevant details on how to use those additional 4-bits and send across a note to you.

0 Libo Luo over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Intellectual 940 points

Hello Karthikeyan,

thanks for the feedback. Could you please double check if ESM3.12 is not cleared by a the CPU reset (triggered in the CPU interconnect self test)? Otherwise, the proposed solution doesn't work.

Thank you and best regards,

Libo

0 KARTHIKEYAN RAJAMANICKAM over 10 years ago in reply to Libo Luo

TI__Genius 11645 points

Hello Libo,

Those registers are intended to be cleared only by Power on Reset and not by the Interconnect Selt-test reset.

0 Libo Luo over 10 years ago in reply to KARTHIKEYAN RAJAMANICKAM

Intellectual 940 points

Hi Karthikeyan,

thank you very much for the confirmation and the good support! I will close this thread.

Best regards,

Libo

Arm-based microcontrollers

Arm-based microcontrollers forum

Question regarding the TMS570LS4357 CPU interconnect self test